参数资料
型号: MC705JP7CPE
厂商: Freescale Semiconductor
文件页数: 119/164页
文件大小: 0K
描述: IC MCU 8BIT 224 BYTES RAM 28PDIP
标准包装: 13
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,温度传感器,WDT
输入/输出数: 22
程序存储器容量: 6KB(6K x 8)
程序存储器类型: OTP
RAM 容量: 224 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 4x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-DIP(0.600",15.24mm)
包装: 管件
Parallel Input/Output
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
58
Freescale Semiconductor
Figure 7-4. Port A I/O Circuit
7.3 Port B
Port B is an 8-bit, general-purpose, bidirectional I/O port with these features:
Programmable pulldown devices
PB0–PB4 are shared with the analog subsystem.
PB3 and PB4 are shared with the 16-bit programmable timer.
PB4 can be driven directly by the output of comparator 1.
PB5–PB7 are shared with the simple serial interface (SIOP).
High current sinking capability on the PB4 pin
High current sourcing capability on the PB4 pin
7.3.1 Port B Data Register
The port B data register (PORTB) contains a bit for each of the port B pins. When a port B pin is
programmed to be an output, the state of its data register bit determines the state of the output pin. When
a port B pin is programmed to be an input, reading the port B data register returns the logic state of the
pin. Reset has no effect on port B data.
Address:
$0001
Bit 7
654321
Bit 0
Read:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Write:
Reset:
Unaffected by reset
Alternate:
SCK
SDI
SDO
AN4
AN3
AN2
AN1
AN0
Alternate:
SCK
SDI
SDO
TCMP
TCAP
AN2
AN1
AN0
Alternate:
SCK
SDI
SDO
CMP1
TCAP
AN2
AN1
AN0
Figure 7-5. Port B Data Register (PORTB)
PAx
EXTERNAL
INTERRUPT
REQUEST
PORT A DATA
REGISTER
BIT PAx
READ $0004
WRITE $0000
READ $0000
WRITE $0010
PULLDOWN
DEVICE
RESET
INTERNA
LD
AT
A
B
U
S
HIGH SINK/SOURCE
CURRENT
SWPD
I
WRITE $0004
DATA DIRECTION
REGISTER A
BIT DDRAx
PULLDOWN
REGISTER A
BIT PDIAx
R
MASK OPTION REG. ($1FF1)
CAPABILITY
(PA0:3)
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