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参数资料
型号： MC705JP7CPE
厂商： Freescale Semiconductor
文件页数： 17/164页
文件大小： 0K
描述： IC MCU 8BIT 224 BYTES RAM 28PDIP
标准包装： 13
系列： HC05
核心处理器： HC05
芯体尺寸： 8-位
速度： 2.1MHz
连通性： SIO
外围设备： POR，温度传感器，WDT
输入/输出数： 22
程序存储器容量： 6KB（6K x 8）
程序存储器类型： OTP
RAM 容量： 224 x 8
电压 - 电源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
数据转换器： A/D 4x12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 28-DIP（0.600"，15.24mm）
包装： 管件
Timer Status Register
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
113
IEDG — Input Capture Edge Select
The state of this read/write bit determines whether a positive or negative transition triggers a transfer
of the contents of the timer register to the input capture register. This transfer can occur due to
transitions on the TCAP pin or the CPF2 flag bit of voltage comparator 2. Resets have no effect on the
IEDG bit.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
NOTE
The IEDG bit must be set when either mode 2 or 3 of the analog subsystem
is being used for A/D conversions. Otherwise, the input capture will not
occur on the rising edge of the comparator 2 flag.
OLVL — Output Compare Output Level Select
The state of this read/write bit determines whether a logic 1 or a logic 0 is transferred to the TCMP pin
when a successful output compare occurs. Reset clears the OLVL bit.
1 = Signal to TCMP pin goes high on output compare.
0 = Signal to TCMP pin goes low on output compare.
11.7 Timer Status Register
The timer status register (TSR) shown in Figure 11-11 contains flags for these events:
An active signal on the TCAP pin or the CPF2 flag bit of voltage comparator 2 in the analog
subsystem, transferring the contents of the timer registers to the input capture registers
A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to
the PB4/AN4/TCMP pin if that pin is set as an output
An overflow of the timer registers from $FFFF to $0000
Writing to any of the bits in the TSR has no effect. Reset does not change the state of any of the flag bits
in the TSR.
ICF — Input Capture Flag
The ICF bit is automatically set when an edge of the selected polarity occurs on the TCAP pin. Clear
the ICF bit by reading the timer status register with the ICF set, and then reading the low byte (ICRL,
$0015) of the input capture registers. Resets have no effect on ICF.
OCF — Output Compare Flag
The OCF bit is automatically set when the value of the timer registers matches the contents of the
output compare registers. Clear the OCF bit by reading the timer status register with the OCF set and
then accessing the low byte (OCRL, $0017) of the output compare registers. Resets have no effect on
OCF.
Address:
$0013
Bit 7
654321
Bit 0
Read:
ICF
OCF
TOF
00000
Write:
Reset:
U
00000
= Unimplemented
U = Unaffected
Figure 11-11. Timer Status Register (TSR)
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