参数资料
型号: MC705JP7CPE
厂商: Freescale Semiconductor
文件页数: 47/164页
文件大小: 0K
描述: IC MCU 8BIT 224 BYTES RAM 28PDIP
标准包装: 13
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,温度传感器,WDT
输入/输出数: 22
程序存储器容量: 6KB(6K x 8)
程序存储器类型: OTP
RAM 容量: 224 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 4x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-DIP(0.600",15.24mm)
包装: 管件
Electrical Specifications
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
140
Freescale Semiconductor
15.5 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc)
15.6 Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc)
Characteristic(1)
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted. All values shown reflect average measurements.
Symbol
Min
Typ(2)
2. Typical values at midpoint of voltage range, 25
°C only
Max
Unit
RUN(3) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 4.2 MHz
3. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all
inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
IDD
150
375
3.00
568
1100
5.20
A
mA
WAIT(4) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 4.2 MHz
4. Wait IDD is affected linearly by the OSC2 capacitance.
IDD
45
75
1.00
85
375
2.20
A
mA
STOP(5) (analog and LVR disabled)
Typical
–40
°C to 85°C
5. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc, OSC1 = VDD.
IDD
2
4
10
20
A
Incremental IDD for enabled modules
LVR
Analog subsystem
IDD
5
380
15
475
A
Characteristic(1)
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted. All values shown reflect average measurements.
Symbol
Min
Typ(2)
2. Typical values at midpoint of voltage range, 25
°C only.
Max
Unit
RUN(3) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 2.1 MHz
3. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all
inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
IDD
70
320
1.25
320
800
2.60
A
mA
WAIT(4) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 2.1 MHz
4. Wait IDD is affected linearly by the OSC2 capacitance.
IDD
20
40
0.50
65
250
1.10
A
mA
STOP(5) (analog and LVR disabled)
25
°C
–40
°C to 85°C
5. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc, OSC1 = VDD.
IDD
1
2
5
10
A
Incremental IDD for enabled modules
LVR
Analog subsystem
IDD
5
380
15
475
A
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