参数资料
型号: MC9328MX21VH
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 266 MHz, MICROPROCESSOR, PBGA289
封装: 17 X 17 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, MAPBGA-289
文件页数: 104/106页
文件大小: 1932K
代理商: MC9328MX21VH
Specifications
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
97
3.21
I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
Figure 80. Definition of Bus Timing for I2C
3.22
CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register
for statistic data generation, a status register, interface logic, a 32
× 32 image data receive FIFO,
and a 16
× 32 statistic data FIFO.
3.22.1
Gated Clock Mode
Figure 81 shows the timing diagram when the CMOS sensor output data is configured for negative
edge and the CSI is programmed to received data on the positive edge. Figure 82 on page 98 shows
the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI
is programmed to received data in negative edge. The parameters for the timing diagrams are listed
in Table 43 on page 98. The formula for calculating the pixel clock rise and fall time is located in
Table 42. I2C Bus Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
SCL Clock Frequency
0
100
0
100
kHz
1
Hold time (repeated) START condition
114.8
111.1
ns
2
Data hold time
0
69.7
0
72.3
ns
3
Data setup time
3.1
1.76
ns
4
HIGH period of the SCL clock
69.7
68.3
ns
5
LOW period of the SCL clock
336.4
335.1
ns
6
Setup time for STOP condition
110.5
111.1
ns
SDA
SCL
1
2
3
4
6
5
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