Signal Descriptions
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
9
SLCDC1_DAT[15:0]
SLCDC Data output signals for connection to a parallel SLCD panel interface. These signals are
multiplexed with LD[15:0] while an alternate 8-bit SLCD muxing is available on LD[15:8]. Further
alternate muxing of these signals are available on some of the USB OTG and USBH1 signals.
SLCDC2_CLK
SLCDC Clock input signal for pass through to SLCD device. This signal is multiplexed with
SSI3_CLK signal from SSI3.
SLCDC2_CS
SLCDC Chip Select input signal for pass through to SLCD device. This signal is multiplexed with
SSI3_TXD signal from SSI3.
SLCDC2_RS
SLCDC Register Select input signal for pass through to SLCD device. This signal is multiplexed
with SSI3_RXD signal from SSI3.
SLCDC2_D0
SLCD Data input signal for pass through to SLCD device. This signal is multiplexed with SSI3_FS
signal from SSI3.
Bus Master Interface (BMI)
BMI_D[15:0]
BMI bidirectional data bus. Bus width is programmable between 8-bit or 16-bit.These signals are
multiplexed with LD[15:0] and SLCDC_DAT[15:0].
BMI_CLK_CS
BMI bidirectional clock or chip select signal.This signal is multiplexed with LSCLK of LCDC.
BMI_WRITE
BMI bidirectional signal to indicate read or write access. This is an input signal when the BMI is a
slave and an output signal when BMI is the master of the interface. BMI_WRITE is asserted for
write and negated for read.This signal is muxed with LD[17] of LCDC.
BMI_READ
BMI output signal to enable data read from external slave device. This signal is not used and
driven high when BMI is slave.This signal is multiplexed with CONTRAST signal of LCDC.
BMI_READ_REQ
BMI Read request output signal to external bus master. This signal is active when the data in the
TXFIFO is larger or equal to the data transfer size of a single external BMI access.This signal is
muxed with LD[16] of LCDC.
BMI_RXF_FULL
BMI Receive FIFO full active high output signal to reflect if the RxFIFO reaches water mark
value.This signal is muxed with VSYNC of the LCDC.
BMI_WAIT
BMI Wait—Active low signal to wait for data ready (read cycle) or accepted (write_cycle). Also
multiplexed with VSYNC.
External DMA
EXT_DMAREQ
External DMA Request input signal. This signal is multiplexed with CSPI1_RDY.
EXT_DMAGRANT
External DMA Grant output signal. This signal is multiplexed with LD[16].
NAND Flash Controller
NF_CLE
NAND Flash Command Latch Enable output signal. This signal is multiplexed with PC_POE of
PCMCIA.
NF_CE
NAND Flash Chip Enable output signal. This signal is multiplexed with PC_CE1 of PCMCIA.
NF_WP
NAND Flash Write Protect output signal. This signal is multiplexed with PC_CE2 of PCMCIA.
NF_ALE
NAND Flash Address Latch Enable output signal. This signal is multiplexed with PC_OE of
PCMCIA.
NF_RE
NAND Flash Read Enable output signal. This signal is multiplexed with PC_RW of PCMCIA.
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes