参数资料
型号: MC9328MX21VH
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 266 MHz, MICROPROCESSOR, PBGA289
封装: 17 X 17 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, MAPBGA-289
文件页数: 32/106页
文件大小: 1932K
代理商: MC9328MX21VH
Specifications
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
31
3.10
LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the i.MX21 Reference
Manual
.
Figure 19. SCLK to LD Timing Diagram
Table 17. Timing Parameter Table for Figure 14 through Figure 18
Ref
No.
Parameter
Minimum
Maximum
Unit
1
SPI_RDY to SS output low
2T 1
1. T = CSPI system clock period (PERCLK2).
–ns
2SS output low to first SCLK edge
3Tsclk 2
2. Tsclk = Period of SCLK.
–ns
3
Last SCLK edge to SS output high
2Tsclk
ns
4SS output high to SPI_RDY low
0
ns
5SS output pulse width
Tsclk + WAIT 3
3. WAIT = Number of bit clocks (SCLK) or 32.768 KHz clocks per Sample Period Control
Register.
–ns
6SS input low to first SCLK edge
T
ns
7SS input pulse width
T
ns
Table 18. LCDC SCLK Timing Parameter Table
Symbol
Parameter
3.0 +/- 0.3V
Unit
Minimum
Maximum
T1
SCLK period
23
2000
ns
T2
Pixel data setup time
11
ns
T3
Pixel data up time
11
ns
The pixel clock is equal to LCDC_CLK / (PCD + 1).
When it is in CSTN, TFT or monochrome mode with bus width = 1, SCLK is equal to the pixel clock.
When it is in monochrome with other bus width settings, SCLK is equal to the pixel clock divided by bus width.
The polarity of SCLK and LD can also be programmed.
Maximum frequency of SCLK is HCLK / 3 for TFT and CSTN, otherwise LD output will be incorrect.
LSCLK
LD[17:0]
T1
T2
T3
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