参数资料
型号: MC9328MX21VH
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 266 MHz, MICROPROCESSOR, PBGA289
封装: 17 X 17 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, MAPBGA-289
文件页数: 40/106页
文件大小: 1932K
代理商: MC9328MX21VH
Specifications
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
39
Figure 26. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 27
on page 39, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by
a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by
the responding card. The other two diagrams show the separating periods NRC and NCC.
Figure 27. Timing Diagrams at Data Transfer Mode
Figure 28 on page 40 shows basic read operation timing. In a read operation, the sequence starts with a
single block read command (which specifies the start address in the argument field). The response is sent
on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC,
beginning from the last bit of the read command. If the system is in multiple block read mode, the card
sends a continuous flow of data blocks with distance NAC until the card sees a stop transmission command.
The data stops two clock cycles after the end bit of the stop command.
SET_RCA Timing
Identification Timing
Host Command
CID/OCR
NID cycles
CMD
Content
S T
E Z
Z S T
Content
Z Z
******
CRC
Z
Host Command
CID/OCR
NCR cycles
CMD
Content
S T
E Z
Z S T
Content
Z Z
******
CRC
Z
Timing of command sequences (all modes)
Timing response end to next CMD start (data transfer mode)
Command response timing (data transfer mode)
Host Command
Response
NCR cycles
CMD
Content
S T
E Z Z P
P S T
Content
CRC
E Z Z
******
CRC
Z
Response
Host Command
NRC cycles
CMD
Content
S T
E Z
Z S T
Content
CRC
E Z Z
******
CRC
Z
Host Command
NCC cycles
CMD
Content
S T
E Z
Z S T
Content
CRC
E Z Z
******
CRC
Z
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