参数资料
型号: MCHC705JJ7CPE
厂商: Freescale Semiconductor
文件页数: 127/164页
文件大小: 0K
描述: IC MCU 8BIT 224 BYTES RAM 20PDIP
标准包装: 18
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,温度传感器,WDT
输入/输出数: 14
程序存储器容量: 6KB(6K x 8)
程序存储器类型: OTP
RAM 容量: 224 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 4x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-DIP(0.300",7.62mm)
包装: 管件
Port B
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
65
7.3.9 PB7/SCK Logic
The PB7/SCK pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as
shown in Figure 7-12. The operations of the PB7/SCK pin are summarized in Table 7-3.
Figure 7-12. PB7/SCK Pin I/O Circuit
When using the PB7/SCK pin, these interactions must be noted:
1.
If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB7/SCK
pin buffer to be controlled by the MSTR control bit in the SCR. The pulldown device is disabled in
these cases.
a.
If the MSTR bit is set, then the PB7/SCK pin buffer will be enabled and driven by the serial
data clock (SCK) from the SIOP.
b.
If the MSTR bit is clear, then the PB7/SCK pin buffer will be disabled, allowing the PB7/SCK
pin to drive the serial data clock (SCK) into the SIOP.
2.
If the SIOP function is in control of the PB7/SCK pin, the DDRB7 and PB7 data register bits are still
accessible to the CPU and can be altered or read without affecting the SIOP functionality.
However, if the DDRB7 bit is cleared, reading the PB7 data register will return the current state of
the PB7/SCK pin.
3.
If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored
in the DDRB7, PDIB7, and PB7 register bits will then control the PB7/SCK pin.
4.
If the PB7/SCK pin is to be a digital input, then both the SPE bit in the SCR and the DDRB7 bit
must be cleared. Depending on the external application, the pulldown device may also be disabled
by setting the PDIB7 pulldown inhibit bit.
DATA DIRECTION
REGISTER B
BIT DDRB7
PORT B DATA
REGISTER
BIT PB7
PULLDOWN
REGISTER B
BIT PDIB7
R
PB7
READ $0005
WRITE $0001
READ $0001
WRITE $0011
PULLDOWN
DEVICE
RESET
IN
T
E
R
N
AL
D
AT
A
BU
S
WRITE $0005
SCK
SERIAL ENABLE (SPE)
CLOCK SOURCE (MSTR)
SERIAL DATA CLOCK (SCK)
SWPDI
MASK OPTION REG. ($1FF1)
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