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参数资料
| 型号： | MKI41T56S00TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封装： | 0.150 INCH, PLASTIC, SOP-8 |
| 文件页数： | 16/16页 |
| 文件大小： | 105K |
| 代理商： | MKI41T56S00TR |
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MK41T56, MKI41T56
WRITE MODE
In this mode the master transmitter transmits to
the MK41T56 slave receiver. Bus protocol is
shown in Figure 10. Following the START condi-
tion and slave address, a logic ’0’ (R/W = 0) is
placed on the bus and indicates to the addressed
device that word address An will follow and is to be
written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next memory location within the RAM on the
reception of an acknowledge clock. The MK41T56
slave receiver will send an acknowledge clock to
the master transmitter after it has received the
slave address and again after it has received the
word address and each data byte (see Figure 9).
READ MODE
In this mode, the master reads the MK41T56 slave
after setting the slave address (see Figure 11).
Following the write mode control bit (R/W = 0) and
the acknowledge bit, the word address An is writ-
ten to the on-chip address pointer. Next the
START condition and slave address are repeated,
followed by the READ mode control bit (R/W = 1).
At this point, the master transmitter becomes the
master receiver. The data byte which was ad-
dressed will be transmitted and the master receiv-
er will send an acknowledge bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an acknowledge bit. The
MK41T56 slave transmitter will now place the data
byte at address An + 1 on the bus. The master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to An + 2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
An alternate READ mode may also be implement-
ed, whereby the master reads the MK41T56 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer, see Figure 12.
CLOCK CALIBRATION
The MK41T56 is driven by a quartz controlled os-
cillator with a nominal frequency of 32,768Hz. A
typical MK41T56 is accurate within ±1minute per
month at 25°C without calibration. The devices are
tested not to exceed 35ppm (parts per million) os-
cillator frequency error at 25°C, which equates to
about ±1.53 minutes per month. The oscillation
rate of any crystal changes with temperature (see
Figure 14).
Most clock chips compensate for crystal frequency
and temperature shift error with cumbersome trim
capacitors. The MK41T56 design, however, em-
ploys periodic counter correction. The calibration
circuit adds or subtracts counts from the oscillator
divider circuit at the divide by 256 stage, as shown
in Figure 13. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits in the Control register. This byte can be set to
represent any value between 0 and 31 in binary
form. The sixth bit is a sign bit; '1' indicates positive
calibration, '0' indicates negative calibration. Cali-
bration occurs within a 64minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles. If a binary '1' is loaded into
the register, only the first 2 minutes in the 64 min-
utes cycle will be modified; if a binary 6 is loaded,
the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034ppm of adjustment per calibration
step in the calibration register. Assuming that the
oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration byte
would represent 10.7 seconds per month.
Figure 10. Slave Address Location
AI00590
R/W
SLAVE ADDRESS
START
A
0
100
0
11
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