- 您现在的位置：买卖IC网 > PDF目录67996 > ML60851CTB (LAPIS SEMICONDUCTOR CO LTD) UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 PDF资料下载
参数资料
| 型号： | ML60851CTB |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件页数： | 22/68页 |
| 文件大小： | 442K |
| 代理商： | ML60851CTB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
PEDL60851C-02
1Semiconductor
ML60851C
28/67
Interrupt Status Register (INTSTAT)
Read address
DCh
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
000
0000
0
After a bus reset
See
below
0
See
below
See
below
0
See
below
00
Definition
Setup Ready Interrupt Status: When bit D0 of the interrupt enable register (INTENBL) is “1”, the content of bit
D0 of the EP0 status register (EP0STAT) is copied here.
This bit is “0” when D0 of INTENBL is “0”. In other words, when the eight bytes of setup
data are received in the setup stage of control transfer and are correctly stored in the setup
registers, this bit is set to “1” and the
INTR pin is asserted.
EP1 Packet Ready Interrupt Status: When bit D1 of the interrupt enable register (INTENBL) is “1”, the negation of
the content of bit D1 or of bit D5 of the end point packet ready register (PKTRDY) is copied
here. This bit is “0” when bit D1 of INTENBL is “0”. The value at the time of a bus reset is
determined based on the value of INTENBL and the EP transfer direction at that time, and
also based on the value of the packet ready bit for that EP.
(If the EP1 transfer direction has been set as “Receive”, the negation of D1 is stored here, and
the negation of D5 is stored if the transfer direction has been set as “Transmit”.)
During data reception, the packet ready interrupt is generated when one packet of receive
data is correctly stored in one of the two FIFO layers of EP1. During transmission, the packet
ready interrupt is generated when data transmission has been completed from (and writing
becomes possible again) one of the two FIFO layers of EP1.
Setup Ready Interrupt Status
EP1 Packet Ready Interrupt
Status
EP2 Packet Ready Interrupt
Status
EP0 Receive Packet Ready
Interrupt Status
EP0 Transmit Packet Ready
Interrupt Status
USB Bus Reset Interrupt Status
Suspend State Interrupt Status
EP3 Packet Ready Interrupt Status
相关PDF资料 |
PDF描述 |
|---|---|
| ML60851CGA | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| ML60851DGA | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| ML60851DTB | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| ML610Q340-XXXMB | 8-BIT, FLASH, 4.2 MHz, RISC MICROCONTROLLER, PDSO30 |
| ML610340-XXXMB | 8-BIT, MROM, 4.2 MHz, RISC MICROCONTROLLER, PDSO30 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ML60851D | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:USB Device Controller |
| ML60851E | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:USB Device Controller |
| ML60851EGA | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:USB Device Controller |
| ML60851ETB | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:USB Device Controller |
| ML60852 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:USB Device Controller |
发布紧急采购，3分钟左右您将得到回复。