- 您现在的位置：买卖IC网 > PDF目录67996 > ML60851CTB (LAPIS SEMICONDUCTOR CO LTD) UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 PDF资料下载
参数资料
| 型号： | ML60851CTB |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件页数： | 37/68页 |
| 文件大小： | 442K |
| 代理商： | ML60851CTB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
PEDL60851C-02
1Semiconductor
ML60851C
41/67
End Point 2 Data Toggle Register (EP2TGL)
Read address
F5h
Write address
75h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
000
0000
0
After a bus reset
000
0000
0
Definition
000
0000
Data Sequence Toggle Bit:
When initializing an EP after receiving a setup packet, write a “1” in this bit to reset
the toggle bit of the data packet and specify PID of DATA0 (this bit also becomes
“0”). Thereafter, the synchronous operation is made automatically based on the data
sequence toggling mechanism.
The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits,
it will be invalid.
End Point 2 Payload Register (EP2PLD)
Read address
F6h
Write address
76h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
xx
xxxx
x
After a bus reset
0
xx
xxxx
x
Definition
0
Maximum packet size (R/W)
Maximum Packet Size:
The value of wMaxPacketSize of the end point descriptor selected by the
Set_Configuration request from the host computer should be written in this register
by the local MCU. The packet size of packets other than short packets is specified in
units of a byte. The value can be one of 40h (64 bytes), 20h (32 bytes), 10h (16
bytes), and 08h (8 bytes). This register is used for EP2 reception. During data
reception by EP2, if a packet with more number of bytes than that specified here is
received, the receive packet ready bit is not asserted, and the stall bit is set during
EOP and the stall handshake is returned to the host computer.
Bit D7 is fixed at “0”, and even if a “1” is written, it will be invalid.
Data Sequence Toggle Bit
(R/Rese
t)
相关PDF资料 |
PDF描述 |
|---|---|
| ML60851CGA | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| ML60851DGA | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| ML60851DTB | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| ML610Q340-XXXMB | 8-BIT, FLASH, 4.2 MHz, RISC MICROCONTROLLER, PDSO30 |
| ML610340-XXXMB | 8-BIT, MROM, 4.2 MHz, RISC MICROCONTROLLER, PDSO30 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ML60851D | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:USB Device Controller |
| ML60851E | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:USB Device Controller |
| ML60851EGA | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:USB Device Controller |
| ML60851ETB | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:USB Device Controller |
| ML60852 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:USB Device Controller |
发布紧急采购，3分钟左右您将得到回复。