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参数资料
| 型号： | ML60851CTB |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件页数： | 36/68页 |
| 文件大小： | 442K |
| 代理商： | ML60851CTB |
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PEDL60851C-02
1Semiconductor
ML60851C
40/67
End Point 2 Control Register (EP2CON)
Read address
F4h
Write address
74
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
1
0
1
0
X
0
After a bus reset
001
010
X
0
Definition
01
010
Configuration Bit: The local MCU should write a “1” in this bit during the status stage of control transfer when a
“Set Configuration” request is received from the host computer to make EP2 active. When this
bit is “1”, the exchange of data between the host computer and EP2 is enabled. When this bit is
“0”, this IC does not respond to any transactions with this EP.
Stall Bit:
During EP2 reception, when a data packet is received with a number of bytes more than the
maximum packet size set in the pay load register EP2PLD, the ML60851C automatically sets
this bit to “1”. It is also possible for the local MCU to write a “1” in this bit. When this bit is
“1”, the stall handshake is automatically returned to the host computer in response to the packet
transmitted by the host computer to the end point. In addition, the packet ready status is not
asserted and the
INTR pin is not asserted.
The EP2 transfer mode is set as a bulk transfer and the end point address is 2h. Therefore, the bits D6 to D2 have
fixed values, and other values written in them are ignored.
Configuration Bit (R/W)
Stall Bit (R/W)
Transfer Type
10 = Bulk transfer
End Point Address (R)
Transfer Direction (R/W)
0 = Receive, 1 = Transmit
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