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参数资料
| 型号： | ML60851CTB |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件页数： | 30/68页 |
| 文件大小： | 442K |
| 代理商： | ML60851CTB |
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PEDL60851C-02
1Semiconductor
ML60851C
35/67
End Point 1 Data Toggle Register (EP1TGL)
Read address
E5h
Write address
65h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
000
0000
0
After a bus reset
000
0000
0
Definition
000
0000
Data Sequence Toggle Bit:
When initializing an EP, write a “1” in this bit to reset the toggle bit of the data
packet and specify PID of DATA0 (this bit also becomes “0”). Thereafter, the
synchronous operation is made automatically based on the data sequence toggling
mechanism.
The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits, it will be invalid.
End Point 1 Payload Register (EP1PLD)
Read address
E6h
Write address
66h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
xx
xxxx
x
After a bus reset
0
xx
xxxx
x
Definition
0
Maximum packet size (R/W)
Maximum Packet Size:
The value of wMaxPacketSize of the end point descriptor selected by the Set_Configuration
request from the host computer should be written in this register by the local MCU.
The packet size of packets other than short packets is specified in units of a byte.
The value can be one of 40h (64 bytes), 20h (32 bytes), 10h (16 bytes), and 08h
(8 bytes).
During data reception by EP1, if a packet with more number of bytes than that
specified here is received, the receive packet ready bit is not asserted, and the stall
bit is set during EOP and the stall handshake is returned to the host computer.
On the other hand, when EP1 is being used for transmission, the transmit packet
ready bit is set automatically when the writing of data of the number of bytes set in
this register (maximum packet size) by the DMA controller is completed.
Bit D7 is fixed at “0”, and even if a “1” is written, it will be ignored.
Data Sequence Toggle Bit
(R/Reset
)
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