参数资料
型号: MPC5606SCMG6
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PBGA208
封装: 17 X 17 MM, 1 MM PITCH, MAPBGA-208
文件页数: 91/134页
文件大小: 890K
代理商: MPC5606SCMG6
MPC560xS Microcontroller Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Overview
Freescale Semiconductor
6
Real Time Counter (RTC) with multiple clock sources:
— 128 kHz slow internal RC oscillator or 16 MHz fast internal RC oscillator supporting autonomous wakeup with
1 ms resolution with maximum timeout of 2 seconds
— 32 KHz slow external crystal oscillator, supporting wakeup with 1 s resolution and maximum timeout of one hour
— 4–16 MHz fast external crystal oscillator
System timers:
— 4-channel 32-bit System Timer Module (STM)—included in processor platform
— 4-channel 32-bit Periodic Interrupt Timer (PIT) module
— Software Watchdog Timer (SWT)
System Integration Unit (SIU) module to manage resets, external interrupts, GPIO and pad control
System Status and Configuration Module (SSCM) to provide information for identification of the device, last boot
mode, or debug status and provides an entry point for the censorship password mechanism
Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified register interface,
enabling access to all clock sources
Clock Monitor Unit (CMU) to monitor the integrity of the main crystal oscillator and the PLL and act as a frequency
meter, measuring the frequency of one clock source and comparing it to a reference clock
Mode Entry Module (MC_ME) to control the device power mode, i.e., RUN, HALT, STOP, or STANDBY, control
mode transition sequences, and manage the power control, voltage regulator, clock generation and clock management
modules
Reset Generation Module (MC_RGM) to manage reset assertion and release to the device at initial power-up
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard
Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator controller for regulating the 3.3 or 5 V supply voltage down to 1.2 V for core logic (requires
external ballast transistor)
The MPC5606S microcontrollers are offered in the following packages:
1
— 144 LQFP, 0.5 mm pitch, 20 mm
20 mm outline
— 176 LQFP, 0.5 mm pitch, 24 mm
24 mm outline
— 208 MAPBGA, 1.0 mm pitch, 17 mm
17 mm outline (not a production package; available in limited quantities
for tool development only)
1.6
Details
1.6.1
Low-power operation
MPC5606S devices are designed for optimized low-power operation and dynamic power management of the core processor and
peripherals. Power management features include software-controlled clock gating of peripherals and multiple power domains
to minimize leakage in low-power modes.
There are two static low-power modes, STANDBY and STOP, and two dynamic power modes—RUN and HALT. Both low
power modes use clock gating to halt the clock for all or part of the device. The STANDBY mode also uses power gating to
automatically turn off the power supply to parts of the device to minimize leakage.
STANDBY mode turns off the power to the majority of the chip to offer the lowest power consumption mode. The contents of
the cores, on-chip peripheral registers and potentially some of the volatile memory are lost. STANDBY mode is configurable
to make certain features available with the disadvantage that these consume additional current:
It is possible to retain the contents of the full RAM or only 8 KB.
1. See the device comparison table or orderable parts summary for package offerings for each device in the family.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC5606S
products
in
208
MAPBGA
packages
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