
MOTOROLA
Chapter 3. Central Processing Unit
3-37
Exception Model
next exception condition is encountered. This method of recognizing and handling
exception conditions sequentially guarantees that the machine state is recoverable and
processing can resume without losing instruction results.
To prevent the loss of state information, exception handlers must save the information
stored in SRR0 and SRR1 soon after the exception is taken to prevent this information from
being lost due to another exception being taken.
3.11.1
Exception Classes
3.11.2
Ordered Exceptions
In the RCPU, all exceptions except for reset, debug port non-maskable interrupts, and
machine check exceptions are ordered. Ordered exceptions satisfy the following criteria:
Only one exception is reported at a time. If, for example, a single instruction
encounters multiple exception conditions, those conditions are encountered
sequentially. After the exception handler handles an exception, instruction execution
continues until the next exception condition is encountered.
When the exception is taken, no program state is lost.
3.11.3
Unordered Exceptions
Unordered exceptions may be reported at any time and are not guaranteed to preserve
program state information. The processor can never recover from a reset exception. It can
recover from other unordered exceptions in most cases. However, if a debug port
non-maskable interrupt or machine check exception occurs during the servicing of a
previous exception, the machine state information in SRR0 and SRR1 (and, in some cases,
the DAR and DSISR) may not be recoverable; the processor may be in the process of saving
or restoring these registers.
To determine whether the machine state is recoverable, the RI (recoverable exception) bit
in SRR1 can be read. During exception processing, the RI bit in the MSR is copied to SRR1
and then cleared. The operating system should set the RI bit in the MSR at the end of each
Table 3-18. RCPU Exception Classes
Class
Exception Type
Asynchronous, unordered
Machine check
System reset
Asynchronous, ordered
External interrupt
Decrementer
Synchronous (ordered, precise)
Instruction-caused exceptions