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MPC561/MPC563 Reference Manual
MOTOROLA
Exception Model
exception handler’s prologue (after saving the program state) and clear the bit at the start
of each exception handler’s epilogue (before restoring the program state). Then, if an
unordered exception occurs during the servicing of an exception handler, the RI bit in SRR1
will contain the correct value.
3.11.4
Precise Exceptions
In the RCPU, all synchronous (instruction-caused) exceptions are precise. When a precise
exception occurs, the processor backs the machine up to the instruction causing the
exception. This ensures that the machine is in its correct architecturally-defined state. The
following conditions exist at the point a precise exception occurs:
1. Architecturally, no instruction following the faulting instruction in the code stream
has begun execution.
2. All instructions preceding the faulting instruction appear to have completed with
respect to the executing processor.
3. SRR0 addresses either the instruction causing the exception or the immediately
following instruction. Which instruction is addressed can be determined from the
exception type and the status bits.
4. Depending on the type of exception, the instruction causing the exception may not
have begun execution, may have partially completed, or may have completed
execution.
3.11.5
Exception Vector Table
The setting of the exception prefix (IP) bit in the MSR determines how exceptions are
vectored. If the bit is cleared, the exception vector table begins at the physical address
0x0000 0000; if IP is set, the exception vector table begins at the physical address
0xFFF0 0000.
Table 3-19 shows the exception vector offset of the first instruction of the
exception handler routine for each exception type.
NOTE
In the MPC561/MPC563, the exception table can additionally
be relocated by the BBC module to internal memory and
reduce the total size required by the exception table (see
Table 3-19. Exception Vector Offset Table
Vector Offset
(hex)
Exception Type
Section
00000
Reserved
—
00100
System reset, NMI interrupt