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参数资料
| 型号： | MPC9600AE |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK DRIVER LV 48-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟驱动器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:21 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
MPC9600 REVISION 6 JANUARY 7, 2013
6
2013 Integrated Device Technology, Inc.
MPC9600 Data Sheet
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
Table 7. AC Characteristics – 48 LQFP (VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, TA = –40°C to +85°C)(1)
1. AC characteristics are applicable over the entire ambient temperature and supply voltage range and are production tested. AC
characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
8 feedback (FSEL_FB = 0)
12 feedback (FSEL_FB = 1)
Static test mode (VCCA = GND)
25
16.67
0
50
33
500
MHz
PLL locked
VCCA = GND
fVCO
VCO Frequency
200
400
MHz
fMAX
Maximum Output Frequency
2 outputs (FSELx = 0)
4 outputs (FSELx = 1)
100
50
200
100
MHz
PLL locked
frefDC
Reference Input Duty Cycle
25
75
%
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
500
1000
mV
LVPECL
VCMR(2)
2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Common Mode Range
PCLK, PCLK (VCC = 3.3 V 5%)
PCLK, PCLK (VCC = 2.5 V 5%)
1.2
VCC –0.8
VCC –0.6
V
LVPECL
tr, tf
CCLK Input Rise/Fall Time
1.0
ns
see Figure 11
t()
Propagation Delay (static phase offset)
CCLK to FB_IN
PECL_CLK to FB_IN
–60
+30
+40
+130
+140
+230
ps
PLL locked
tsk(o)
Output-to-Output Skew
all outputs, single frequency
all outputs, multiple frequency
within QAx output bank
within QBx outputs
within QCx outputs
70
30
40
30
150
75
125
75
ps
Measured at
coincident rising
edge
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
see Figure 11
tPLZ, HZ
Output Disable Time
10
ns
tPZL, ZH
Output Enable Time
10
ns
BW
PLL Closed Loop Bandwidth
8 feedback (FSEL_FB=0)
12 feedback (FSEL_FB=1)
1.0 – 10
0.6 – 4.0
MHz
–3 dB point of PLL
transfer
characteristic
tJIT(CC)
Cycle-to-Cycle Jitter(3)
All outputs in
2 configuration
All outputs in
4 configuration
40
130
180
ps
Refer to
application
section for other
configurations
tJIT(PER)
Period Jitter(3)
All outputs in
2 configuration
All outputs in
4 configuration
3. Cycle-to-cycle and period jitter depends on output divider configuration.
25
20
70
100
ps
Refer to
application
section for other
configurations
tJIT()
I/O Phase Jitter (1
)VCC = 3.3 V
VCC = 2.5 V
17(4)
4. See Applications Information section for max I/O phase jitter versus frequency.
ps
RMS value at
fVCO = 400 MHz
tLOCK
Maximum PLL Lock Time
5.0
ms
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