- 您现在的位置：买卖IC网 > PDF目录2099 > MPC9600AE (IDT, Integrated Device Technology Inc)IC PLL CLK DRIVER LV 48-LQFP PDF资料下载
参数资料
| 型号： | MPC9600AE |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 15/15页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK DRIVER LV 48-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟驱动器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:21 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
MPC9600 REVISION 6 JANUARY 7, 2013
9
2013 Integrated Device Technology, Inc.
MPC9600 Data Sheet
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
Power Supply Filtering
The MPC9600 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if this
noise is seen on the power supply pins. Random noise on the
VCCA (PLL) power supply impacts the device characteristics, for
instance I/O jitter. The MPC9600 provides separate power
supplies for the output buffers (VCC) and the phase-locked loop
(VCCA) of the device.The purpose of this design technique is to
isolate the high switching noise digital outputs from the relatively
sensitive internal analog phase-locked loop. In a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required. The
simple but effective form of isolation is a power supply filter on the
supply filter scheme. The MPC9600 frequency and phase stability
is most susceptible to noise with spectral content in the 100 kHz
to 20 MHz range. Therefore the filter should be designed to target
this range. The key parameter that needs to be met in the final
filter design is the DC voltage drop across the series filter resistor
RF. From the data sheet the ICCA current (the current sourced
through the VCCA pin) is typically 3 mA (5 mA maximum),
assuming that a minimum of 2.325 V (VCC =3.3 V or VCC =2.5 V)
must be maintained on the VCCA pin. The resistor RF shown in
(VCC = 2.5 V) to meet
the voltage drop criteria.
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter should
provide an attenuation greater than 40 dB for noise whose
spectral content is above 100 kHz. In the example RC filter shown
in Figure 5, the filter cut-off frequency is around 3-5 kHz and the
noise attenuation at 100 kHz is better than 42 dB.
Figure 5. VCCA Power Supply Filter
As the noise frequency crosses the series resonant point of an
individual capacitor its overall impedance begins to look inductive
and thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance path
to ground exists for frequencies well above the bandwidth of the
PLL. Although the MPC9600 has several design features to
minimize the susceptibility to power supply noise (isolated power
and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded due
to system power supply noise. The power supply filter schemes
discussed in this section should be adequate to eliminate power
supply noise related problems in most designs.
Using the MPC9600 in Zero-Delay Applications
Nested clock trees are typical applications for the MPC9600.
For these applications the MPC9600 offers a differential LVPECL
clock input pair as a PLL reference. This allows for the use of
differential LVPECL primary clock distribution devices such as the
Freescale Semiconductor MC100ES6111 or MC100ES6226,
taking advantage of its superior low-skew performance. Clock
trees using LVPECL for clock distribution and the MPC9600 as
LVCMOS PLL fanout buffer with zero insertion delay will show
significantly lower clock skew than clock distributions developed
from CMOS fanout buffers.
The external feedback option of the MPC9600 PLL allows for
its use as a zero delay buffer. The PLL aligns the feedback clock
output edge with the clock input reference edge and virtually
eliminates the propagation delay through the device.
The remaining insertion delay (skew error) of the MPC9600 in
zero-delay applications is measured between the reference clock
input and any output. This effective delay consists of the static
phase offset (SPO or t()), I/O jitter (tJIT(), phase or long-term
jitter), feedback path delay and the output-to-output skew (tSK(O))
relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC9600 zero delay buffer supports applications where
critical clock signal timing can be maintained across several
devices. If the reference clock inputs (CCLK or PCLK) of two or
more MPC9600 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay and
I/O (phase) jitter:
Figure 6. MPC9600 Maximum Device-to-Device Skew
VCCA
VCC
MPC9600
10 nF
CF
RF
VCC
33...100 nF
RF = 9–10 for VCC = 2.5 V or VCC = 3.3 V
CF = 22 F for VCC = 2.5 V or VCC = 3.3 V
tPD,LINE(FB)
tJIT()
+tSK(O)
—t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
TCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
相关PDF资料 |
PDF描述 |
|---|---|
| MPC961CAC | IC BUFFER ZD 1:18 PLL 32-LQFP |
| MPC961PAC | IC BUFFER ZD 1:18 PLL 32-LQFP |
| MPC9653AAC | IC PLL CLK GEN 1:8 3.3V 32-LQFP |
| MPC9658AC | IC PLL CLK GEN 1:10 3.3V 32-LQFP |
| MPC9772FA | IC PLL CLK GEN 1:12 3.3V 52-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9600AER2 | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC9600FA | 功能描述:IC CLOCK DRVR PLL LV 1:21 48LQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MPC9608 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:1:10 LVCMOS Zero Delay Clock Buffer |
| MPC9608AC | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC9608ACR2 | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。