参数资料
型号: MPC9600AE
厂商: IDT, Integrated Device Technology Inc
文件页数: 3/15页
文件大小: 0K
描述: IC PLL CLK DRIVER LV 48-LQFP
标准包装: 250
类型: PLL 时钟驱动器
PLL: 带旁路
输入: LVCMOS,LVPECL
输出: LVCMOS
电路数: 1
比率 - 输入:输出: 2:21
差分 - 输入:输出: 是/无
频率 - 最大: 200MHz
除法器/乘法器: 是/是
电源电压: 2.375 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-TQFP(7x7)
包装: 托盘
MPC9600 REVISION 6 JANUARY 7, 2013
11
2013 Integrated Device Technology, Inc.
MPC9600 Data Sheet
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
At the load end the voltage will double due to the near unity
reflection coefficient, to 2.6 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in this
case 4.0 ns).
Figure 9. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation in
Figure 10 should be used. In this case the series terminating
resistors are reduced such that when the parallel combination is
added to the output buffer impedance the line impedance is
perfectly matched.
Figure 10. Optimized Dual Line Termination
The following figures illustrate the measurement reference for
the MPC9600 clock driver circuit.
Figure 11. CCLK MPC9600 AC Test Reference
Figure 12. PCLK MPC9600 AC Test Reference
Vo
ltage
(V)
OutB
tD = 3.9386
OutA
tD = 3.8956
In
2
4
6
8
10
12
14
Time (ns)
3.0
2.5
2.0
1.5
1.0
0.5
0
ZO = 50
14
MPC9600
Output
Buffer
RS = 22
14
+ 22 || 22 = 50 || 50
25
= 25
Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC9600 DUT
VTT
Differential Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC9600 DUT
VTT
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