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参数资料
| 型号： | MT28F200B5 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | FLASH MEMORY |
| 中文描述： | 闪存 |
| 文件页数： | 11/31页 |
| 文件大小： | 558K |
| 代理商： | MT28F200B5 |
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11
2Mb Smart 3 Boot Block Flash Memory
F48.p65 – Rev. 1/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb
SMART 3 BOOT BLOCK FLASH MEMORY
COMMAND SET
To simplify writing of the memory blocks, the
MT28F002B3 and MT28F200B3 incorporate an ISM
that controls all internal algorithms for the WRITE and
ERASE cycles. An 8-bit command set is used to control
the device. Details on how to sequence commands are
provided in the Command Execution section. Table 1
lists the valid commands.
ISM STATUS REGISTER
The 8-bit ISM status register (see Table 2) is polled to
check for WRITE or ERASE completion or any related
errors. During or following a WRITE, ERASE or ERASE
SUSPEND, a READ operation will output the status
register contents on DQ0-DQ7 without prior com-
mand. While the status register contents are read, the
outputs will not be updated if there is a change in the
ISM status unless OE# or CE# is toggled. If the device is
not in the write, erase, erase suspend or status register
read mode, READ STATUS REGISTER (70H) can be
issued to view the status register contents.
All of the defined bits are set by the ISM, but only the
ISM and erase suspend status bits are reset by the ISM.
The erase, write and V
PP
status bits must be cleared
using CLEAR STATUS REGISTER. If the V
PP
status bit
(SR3) is set, the CEL will not allow further WRITE or
ERASE operations until the status register is cleared.
This allows the user to choose when to poll and clear
the status register. For example, the host system may
perform multiple BYTE WRITE operations before check-
ing the status register instead of checking after each
individual WRITE. Asserting the RP# signal or powering
down the device will also clear the status register.
Table 2
Status Register
STATUS
BIT #
SR7
STATUS REGISTER BIT
ISM STATUS
1 = Ready
0 = Busy
ERASE SUSPEND STATUS
1 = ERASE suspended
0 = ERASE in progress/completed
ERASE STATUS
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
WRITE STATUS
1 = WORD/BYTE WRITE error
0 = Successful WORD/
BYTE WRITE
V
PP
STATUS
1 = No V
PP
voltage detected
0 = V
PP
present
DESCRIPTION
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this
bit to determine when the erase and write status bits are valid.
Issuing an ERASE SUSPEND places the ISM in the suspend mode
and sets this and the ISMS bit to “1.” The ESS bit will remain “1” until
an ERASE RESUME is issued.
ES is set to “1” after the maximum number of ERASE cycles is
executed by the ISM without a successful verify. ES is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
SR6
SR5
SR4
SR3
V
PP
S detects the presence of a V
PP
voltage. It does not monitor V
PP
continuously, nor does it indicate a valid V
PP
voltage. The V
PP
pin is
sampled for 3.3V or 5V after WRITE or ERASE CONFIRM is given. V
PP
S
must be cleared by CLEAR STATUS REGISTER or by a RESET.
Reserved for future use.
SR0-2
RESERVED
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT28F200B5SG-6 B | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 60ns 44-Pin SOP Tray |
| MT28F200B5SG-6 T | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 60ns 44-Pin SOP Tray |
| MT28F200B5SG-8 B TR | 制造商:Micron Technology Inc 功能描述:Flash Mem Parallel 5V 2M-Bit 256K x 8/128K x 16 80ns 44-Pin SOP T/R |
| MT28F320A18 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:FLASH MEMORY |
| MT28F320J3 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Q-FLASHTM MEMORY |
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