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参数资料
| 型号： | MT28F200B5 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | FLASH MEMORY |
| 中文描述： | 闪存 |
| 文件页数： | 4/31页 |
| 文件大小： | 558K |
| 代理商： | MT28F200B5 |
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4
2Mb Smart 3 Boot Block Flash Memory
F48.p65 – Rev. 1/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
NUMBERS
NUMBERS
43
9
NUMBERS
11
SYMBOL
WE#
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle. If
WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if V
PP
=
V
PPH
1
(3.3V), V
PPH
2
(5V) or V
PPH
3
(12V)
1
and RP# = V
IH
during a
WRITE or ERASE. Does not affect WRITE or ERASE operation
on other blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status register,
sets the internal state machine (ISM) to the array read mode
and places the device in deep power-down mode. All inputs,
including CE#, are “Don’t Care,” and all outputs are High-Z.
RP# unlocks the boot block and overrides the condition of
WP# when at V
HH
(12V); RP# must be held at V
IH
during all
other modes of operation.
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active through
DQ8-DQ15. If BYTE# = LOW, DQ8-DQ14 are High-Z, and all
data is accessed through DQ0-DQ7. DQ15/(A - 1) becomes the
least significant address input.
Address Inputs: Select a unique, 16-bit word or 8-bit byte. The
DQ15/(A - 1) input becomes the lowest order address when
BYTE# = LOW (MT28F200B3) to allow for a selection of an
8-bit byte from the 262,144 available.
2
12
14
WP#
Input
12
22
26
CE#
Input
44
10
12
RP#
Input
14
24
28
OE#
Input
33
–
47
BYTE#
Input
11, 10, 9, 8,
7, 6, 5, 4,
42, 41, 40,
39, 38, 37,
36, 35, 34
31
21, 20, 19,
18, 17, 16,
15, 14, 8, 7,
36, 6, 5, 4,
3, 2, 1, 40
–
25, 24, 23,
22, 21, 20,
19, 18, 8, 7,
6, 5, 4, 3, 2,
1, 48
45
A0-A16/
(A17)
Input
DQ15/
(A - 1)
Input/
Output LSB of address input when BYTE# = LOW during READ or
WRITE operation.
Input/
Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE. These pins are used to input
commands to the CEL.
Input/
Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE when BYTE# = HIGH. These
pins are High-Z when BYTE# is LOW.
Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM
until completion of the WRITE or ERASE, V
PP
must be at V
PPH
1
(3.3V), V
PPH
2
(5V) or V
PPH
3
(12V)
1
. V
PP
= “Don’t Care” during all
other operations. (V
PPH
1
is only supported in the commercial
temperature range.)
Supply Power Supply: +3.3V
±
0.3V.
Supply Ground.
–
No Connect: These pins may be driven or left unconnected.
Data I/O: MSB of data when BYTE# = HIGH. Address Input:
15, 17, 19,
21, 24, 26,
28, 30
16, 18, 20,
22, 25, 27,
29
1
25-28, 32-35
29, 31, 33,
35, 38, 40,
42, 44
30, 32, 34,
36, 39, 41,
43
13
DQ0-DQ7
–
DQ8-DQ14
11
V
PP
23
30, 31
23, 39
37
V
CC
V
SS
NC
13, 32
3
27, 46
13, 29, 37, 38 9, 10, 15-17
NOTE:
1. For SmartVoltage-compatible production programming, 12V V
PP
is supported for a maximum of 100 cycles and may
be connected for up to 100 cumulative hours.
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相关代理商/技术参数 |
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|---|---|
| MT28F200B5SG-6 B | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 60ns 44-Pin SOP Tray |
| MT28F200B5SG-6 T | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 60ns 44-Pin SOP Tray |
| MT28F200B5SG-8 B TR | 制造商:Micron Technology Inc 功能描述:Flash Mem Parallel 5V 2M-Bit 256K x 8/128K x 16 80ns 44-Pin SOP T/R |
| MT28F320A18 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:FLASH MEMORY |
| MT28F320J3 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Q-FLASHTM MEMORY |
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