- 您现在的位置：买卖IC网 > PDF目录385639 > MT46V2M32LG (Micron Technology, Inc.) DOUBLE DATA RATE DDR SDRAM PDF资料下载
参数资料
| 型号： | MT46V2M32LG |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 13/65页 |
| 文件大小： | 2360K |
| 代理商： | MT46V2M32LG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页
13
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the DDR SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) REFRESH in FPM/EDO DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 64Mb x32
DDR SDRAM requires AUTO REFRESH cycles at an
average interval of 7.8μs (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the abso-
lute refresh interval is provided. A maximum of eight
AUTO REFRESH commands can be posted to any given
DDR SDRAM, meaning that the maximum absolute
interval between any AUTO REFRESH command and
the next AUTO REFRESH command is 9 × 7.8μs (70.2μs).
This maximum absolute interval is to allow future sup-
port for DLL updates internal to the DDR SDRAM to be
restricted to AUTO REFRESH cycles, without allowing
excessive drift in
t
AC between updates.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). The
DLL is automatically disabled upon entering SELF RE-
FRESH and is automatically enabled upon exiting SELF
REFRESH (200 clock cycles must then occur before a
READ command can be issued). Input signals except
CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting self refresh requires a se-
quence of commands. First, CK must be stable prior to
CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for
t
XSNR
because time is required for the completion of any in-
ternal refresh in progress. A simple algorithm for meet-
ing both refresh and DLL requirements is to apply
NOPs for 200 clock cycles before applying any other
command.
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V2M32V1 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4-1 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75L | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75Z | DOUBLE DATA RATE DDR SDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V2M32V1 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16 | 制造商:Micron Technology Inc 功能描述:32MX16 DDR SDRAM PLASTIC IND TEMP BGA 2.6V DDR - Trays |
| MT46V32M16-5B | 制造商:Micron Technology Inc 功能描述: |
发布紧急采购，3分钟左右您将得到回复。