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参数资料
| 型号： | MT46V2M32LG |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 14/65页 |
| 文件大小： | 2360K |
| 代理商： | MT46V2M32LG |
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14
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
Operations
BANK/ROW
ACTIVATION
Before any READ or WRITE commands can be is-
sued to a bank within the DDR SDRAM, a row in that
bank must be “opened.” This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 4.
After a row is opened with an ACTIVE command, a
READ or WRITE command may be issued to that row,
subject to the
t
RCD specification.
t
RCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a
t
RCD specifi-
cation of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks rounded to 3. This is reflected in Figure 5,
which covers any case where 2 <
t
RCD (MIN)/
t
CK
≤
3.
(Figure 5 also shows the same case for
t
RCD; the same
procedure is used to convert other specification limits
from time units to clock cycles).
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
t
RC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
RRD.
Figure 5
Example: Meeting
t
RCD (
t
RRD) MIN When 2 <
t
RCD (
t
RRD) MIN/
t
CK < 3
Figure 4
Activating a Specific Row in
a Specific Bank
CS#
WE#
CAS#
RAS#
CKE
A0-A10
RA
RA = Row Address
BA = Bank Address
HIGH
BA0,1
BA
CK
CK#
COMMAND
BA0, BA1
ACT
ACT
NOP
tRRD
tRCD
CK
CK#
Bank
x
Bank
y
A0-A10
Row
Row
NOP
RD/WR
NOP
Bank
y
Col
NOP
T0
T1
T2
T3
T4
T5
T6
T7
DON
’
T CARE
NOP
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相关代理商/技术参数 |
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