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| 型号： | MT46V2M32LG |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 50/65页 |
| 文件大小： | 2360K |
| 代理商： | MT46V2M32LG |
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50
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
NOTES (continued)
37. Reduced Output Drive Curves:
a)The full variation in driver pull-down current
from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figures E and F.
b)The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figures E and F.
c) The full variation in driver pull-up current from
minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figures G and H.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figures G and H.
e)The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
will not exceed 1.7, for device drain-to-source
voltages from 0 to V
DD
Q/2.
f) The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10%, for device drain-to-source voltages from
0 to 0.1V to 1.0V.
38. The voltage levels used are derived from the
referenced test load. In practice, the voltage
levels obtained from a properly terminated bus
will provide significantly different voltage values.
39. V
IH
overshoot: VIH (MAX) = V
DD
Q+1.5V for a pulse
width
≤
3ns and the pulse width can not be
greater than 1/3 of the cycle rate. V
IL
undershoot:
V
IL
(MIN) = -1.5V for a pulse width
≤
3ns and the
pulse width can not be greater than 1/3 of the
cycle rate.
40. CKE must be active (high) during the entire time
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge,
until
t
REF later.
41. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset
and followed by a 200 clock cycle delay.
42. V
DD
and V
DD
Q must track each other.
43. Will slightly adjust with V
DD
/V
DD
Q level.
44. During initialization, V
DD
Q, V
TT,
and V
REF
must be
equal to or less than V
DD
+ 0.3V. Alternatively, V
TT
may be 1.35V maximum during power up, even if
V
DD
/V
DD
Q are 0 volts, provided a minimum of 42
ohms or series resistance is used between the V
TT
supply and the input pin.
45.
t
RCD
≤
t
RAP
Figure E
Pull-Down Characteristics
80
I
O
V
OUT
(V)
Nominal low
Minimum
Nominal high
Maximum
70
60
50
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
Figure G
Pull-Up Characteristics
0
I
O
Nominal low
Minimum
Nominal high
Maximum
-20
-40
-60
-80
-100
-120
0.0
0.5
1.0
1.5
2.0
2.5
V
DD
Q - V
OUT (V)
Figure F
Pull-Down Characteristics
I
O
V
OUT
(V)
Nominal low
Minimum
Nominal high
Maximum
50
40
30
20
10
0
0.0
0.2
0.1
0.3
0.4
0.5
0.7
0.6
0.8
0.9
1.0
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