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参数资料
| 型号： | MT48LC4M16A2 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 22/55页 |
| 文件大小： | 1458K |
| 代理商： | MT48LC4M16A2 |
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22
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2003, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
t
WR after the clock edge at which the last desired input
data element is registered. The auto precharge mode
requires a
t
WR of at least one clock plus time, regardless
of frequency. In addition, when truncating a WRITE
burst, the DQM signal must be used to mask input data
for the clock edge prior to, and the clock edge coinci-
dent with, the PRECHARGE command. An example is
shown in Figure 18. Data
n
+ 1 is either the last of a burst
of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
t
RP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
Figure 18
WRITE to PRECHARGE
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
subsequent READ command. Once the READ com-
mand is registered, the data inputs will be ignored, and
WRITEs will not be executed. An example is shown in
Figure 17. Data
n
+ 1 is either the last of a burst of two or
the last desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
Figure 17
WRITE to READ
Figure 16
Random WRITE Cycles
DON’T CARE
DQM
CLK
DQ
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BANK
a
,
COL
n
T5
NOP
WRITE
PRECHARGE
NOP
NOP
D
IN
n
D
IN
n
+ 1
ACTIVE
tRP
BANK
(
a
or all)
t
WR
BANK
a
,
ROW
DQM
DQ
COMMAND
ADDRESS
BANK
a
,
COL
n
NOP
WRITE
PRECHARGE
NOP
NOP
D
IN
n
D
IN
n
+ 1
ACTIVE
tRP
BANK
(
a
or all)
t
WR
NOTE:
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
BANK
a
,
ROW
T6
NOP
NOP
tWR @ tCLK
≥
15ns
tWR = tCLK < 15ns
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
WRITE
BANK,
COL
n
D
IN
n
D
IN
n
+ 1
D
OUT
b
READ
NOP
NOP
BANK,
COL
b
NOP
D
OUT
b
+ 1
T4
T5
TRANSITIONING DATA
DON’T CARE
CLK
DQ
D
IN
n
T2
T1
T3
T0
COMMAND
ADDRESS
WRITE
BANK,
COL
n
D
IN
a
D
IN
x
D
IN
m
WRITE
WRITE
WRITE
BANK,
COL
a
BANK,
COL
x
BANK,
COL
m
TRANSITIONING DATA
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