参数资料
型号: MT48LC4M16A2
厂商: Micron Technology, Inc.
英文描述: SYNCHRONOUS DRAM
中文描述: 同步DRAM
文件页数: 45/55页
文件大小: 1458K
代理商: MT48LC4M16A2
45
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2003, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
ALTERNATING BANK READ ACCESSES
1
TIMING PARAMETERS
-6
-7E
-75
-8E
SYMBOL* MIN MAX
t
AC(3)
t
AC(2)
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
t
CKS
MIN MAX
MIN MAX
MIN MAX UNITS
6
6
1
2
3
3
8
10
1
2
5.5
5.4
5.4
5.4
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
1.5
2.5
2.5
6
1
1.5
t
CMH
t
CMS
t
LZ
t
OH
t
RAS
t
RC
t
RCD
t
RP
t
RRD
1
0.8
1.5
1
3
37
60
15
15
14
0.8
1.5
1
3
44 120,000
66
20
20
15
1
2
1
3
50
70
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
1
2
42
60
18
18
12
120,000
120,000
120,000
ENABLE AUTO PRECHARGE
tCH
tCL
tCK
tAC
tLZ
DQM /
DQML, DQMH
CLK
A0-A9, A11
DQ
BA0, BA1
A10
tOH
D
OUT
m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
ROW
ROW
DON’T CARE
UNDEFINED
tOH
D
OUT
m
+ 3
tAC
tOH
tAC
tOH
tAC
D
OUT
m
+ 2
D
OUT
m
+ 1
COMMAND
tCMH
tCMS
NOP
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
tOH
D
OUT
b
tAC
tAC
READ
ENABLE AUTO PRECHARGE
ROW
ACTIVE
ROW
BANK 0
BANK 0
BANK 3
BANK 3
BANK 0
CKE
tCKH
tCKS
COLUMN
m
2
COLUMN
b
2
T0
T1
T2
T4
T3
T5
T6
T7
T8
tRP - BANK 0
tRAS - BANK 0
t
RC - BANK 0
tRCD - BANK 0
tRCD - BANK 0
CAS Latency - BANK 0
tRCD - BANK 3
CAS Latency - BANK 3
t
RRD
*CAS latency indicated in parentheses.
-6
-7E
-75
-8E
SYMBOL* MIN MAX
MIN MAX
MIN MAX
MIN MAX UNITS
NOTE:
1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A8, A9 and A11 = “ Don’t Care”
x8: A9 and A11 = “ Don’t Care”
x4: A11 = “ Don’t Care”
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