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参数资料
| 型号： | MT48LC4M16A2 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 26/55页 |
| 文件大小： | 1458K |
| 代理商： | MT48LC4M16A2 |
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26
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2003, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
Figure 26
WRITE With Auto Precharge Interrupted by a READ
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
precharge): A READ to bank
m
will interrupt a WRITE
on bank
n
when registered, with the data-out appear-
ing CAS latency later. The PRECHARGE to bank
n
will
begin after
t
WR is met, where
t
WR begins when the
READ to bank
m
is registered. The last valid WRITE to
bank
n
will be data-in registered one clock prior to the
READ to bank
m
(Figure 26).
4. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank
m
will interrupt a WRITE
on bank
n
when registered. The PRECHARGE to bank
n
will begin after
t
WR is met, where
t
WR begins when
the WRITE to bank
m
is registered. The last valid data
WRITE to bank
n
will be data registered one clock prior
to a WRITE to bank
m
(Figure 27).
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK
n
NOP
NOP
NOP
NOP
D
IN
d
+ 1
D
IN
d
D
IN
a
+ 1
D
IN
a
+ 2
D
IN
a
D
IN
d
+ 2
D
IN
d
+ 3
NOP
T7
BANK
n
BANK
m
ADDRESS
NOP
NOTE:
1. DQM is LOW.
BANK
n
,
COL
a
BANK
m
,
COL
d
WRITE - AP
BANK
m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
WRITE with Burst of 4
Write-Back
WR - BANK
n
tRP - BANK
n
tWR - BANK
m
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK
n
NOP
NOP
NOP
NOP
D
IN
a
+ 1
D
IN
a
NOP
NOP
T7
BANK
n
BANK
m
ADDRESS
NOTE:
1. DQM is LOW.
BANK
n
,
COL
a
BANK
m
,
COL
d
READ - AP
BANK
m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
READ with Burst of 4
t
tRP - BANK
m
D
OUT
d
D
OUT
d
+ 1
CAS Latency = 3 (BANK
m
)
RP - BANK
n
WR - BANK
n
TRANSITIONING DATA
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