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参数资料
| 型号： | MT48LC8M8A2TG-8EL:GIT |
| 元件分类： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 18/55页 |
| 文件大小： | 1454K |
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25
64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the
SDRAM
supports
CONCURRENT
AUTO
PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is regis-
tered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered
(Figure 25).
Figure 24
READ With Auto Precharge Interrupted by a READ
Figure 25
READ With Auto Precharge Interrupted by a WRITE
CLK
DQ
DOUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
NOP
DIN
d + 1
DIN
d
DIN
d + 2
DIN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
Idle
NOP
DQM
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page
Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
WRITE with Burst of 4
Write-Back
RP - BANK n
t WR - BANK m
CAS Latency = 3 (BANK n)
READ - AP
BANK n
1
DON’T CARE
TRANSITIONING DATA
DON’T CARE
CLK
DQ
DOUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
READ - AP
BANK n
NOP
DOUT
a + 1
DOUT
d
DOUT
d + 1
NOP
T7
BANK n
CAS Latency = 3 (BANK m)
BANK m
ADDRESS
Idle
NOP
NOTE: DQM is LOW.
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
READ with Burst of 4
Precharge
RP - BANK n
tRP - BANK m
CAS Latency = 3 (BANK n)
TRANSITIONING DATA
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| MT48NSX | 功能描述:插线板 1/4" LF SLDR BAY 1RU, 2X24, NORM STR RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
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