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参数资料
| 型号： | MT48LC8M8A2TG-8EL:GIT |
| 元件分类： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 54/55页 |
| 文件大小： | 1454K |
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8
64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
FUNCTIONAL DESCRIPTION
In general, the 64Mb SDRAMs (4 Meg x 4 x 4 banks,
2 Meg x 8 x 4 banks and 1 Meg x 16 x 4 banks) are quad-
bank DRAMs which operate at 3.3V and include a syn-
chronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the x4’s
16,777,216-bit banks is organized as 4,096 rows by 1,024
columns by 4 bits. Each of the x8’s 16,777,216-bit banks
is organized as 4,096 rows by 512 columns by 8 bits.
Each of the x16’s 16,777,216-bit banks is organized as
4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0 and BA1
select the bank, A0-A11 select the row). The address
bits (x4: A0-A9; x8: A0-A8; x16: A0-A7) registered coinci-
dent with the READ or WRITE command are used to
select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be ini-
tialized. The following sections provide detailed infor-
mation covering device initialization, register defini-
tion, command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to VDD and VDDQ (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100s delay
prior to issuing any command other than a COMMAND
INHIBIT or a NOP. Starting at some point during this
100s period and continuing at least through the end
of this period, COMMAND INHIBIT or NOP commands
should be applied.
Once the 100s delay has been satisfied with at
least one COMMAND INHIBIT or NOP command hav-
ing been applied, a PRECHARGE command should be
applied. All banks must be precharged, thereby plac-
ing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
Register Definition
MODE REGISTER
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode and a write burst mode, as
shown in Figure 1. The mode register is programmed
via the LOAD MODE REGISTER command and will re-
tain the stored information until it is programmed again
or the device loses power.
Mode register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the WRITE
burst mode, and M10 and M11 are reserved for future
use.
The mode register must be loaded when all banks
are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating
either of these requirements will result in unspecified
operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 1. The burst length determines the
maximum number of column locations that can be ac-
cessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types, and a full-
page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
lected by A1-A9 (x4), A1-A8 (x8) or A1-A7 (x16) when the
burst length is set to two; by A2-A9 (x4), A2-A8 (x8) or
A2-A7 (x16) when the burst length is set to four; and by
A3-A9 (x4), A3-A8 (x8) or A3-A7 (x16) when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. Full-page bursts wrap within the
page if the boundary is reached.
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| MT48LCM32B2P | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SDR SDRAM MT48LC2M32B2 a?? 512K x 32 x 4 Banks |
| MT48NN | 功能描述:插线板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
| MT48NNX | 功能描述:插线板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
| MT48NS | 功能描述:插线板 1 RU PANEL 48 LF JA RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
| MT48NSX | 功能描述:插线板 1/4" LF SLDR BAY 1RU, 2X24, NORM STR RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
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