- 您现在的位置：买卖IC网 > PDF目录296642 > MT48LC8M8A2TG-8EL:GIT 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 PDF资料下载
参数资料
| 型号： | MT48LC8M8A2TG-8EL:GIT |
| 元件分类： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 53/55页 |
| 文件大小： | 1454K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页第55页
7
64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
38
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
37
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN
(row active in any bank) or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
19
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
16, 17, 18
WE#, CAS#,
Input
Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the
RAS#
command being entered.
39
x4, x8: DQM
Input
Input/Output Mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
15, 39
x16: DQML,
DQM is sampled HIGH during a WRITE cycle. The output buffers are
DQMH
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC
and DQMH is DQM. On the x16, DQML corresponds to DQ0-DQ7 and
DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered
same state when referenced as DQM.
20, 21
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
23-26, 29-34, 22, 35
A0-A11
Input
Address Inputs: A0-A11 are sampled during the ACTIVE command
(row-address A0-A11) and READ/WRITE command (column-address A0-
A9 [x4]; A0-A8 [x8]; A0-A7 [x16]; with A10 defining auto precharge) to
select one location out of the memory array in the respective bank.
A10 is sampled during a PRECHARGE command to determine if all
banks are to be precharged (A10[HIGH]) or bank selected by BA0,
BA1 (A1[LOW]). The address inputs also provide the op-code
during a LOAD MODE REGISTER command.
2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0-DQ15 x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are
44, 45, 47, 48, 50, 51, 53
NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for x4).
2, 5, 8, 11, 44, 47, 50, 53
DQ0-DQ7
x8: I/O
Data Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for x4).
5, 11, 44, 50
DQ0-DQ3
x4: I/O
Data Input/Output: Data bus for x4.
40
NC
–
No Connect: These pins should be left unconnected.
36
N C
–
Address input (A12) for the 256Mb and 512Mb devices
3, 9, 43, 49
VDDQ
Supply DQ Power: Isolated DQ power on the die for improved noise immunity.
6, 12, 46, 52
VSSQ
Supply DQ Ground: Isolated DQ ground on the die for improved noise
immunity.
1, 14, 27
VDD
Supply Power Supply: +3.3V ±0.3V.
28, 41, 54
VSS
Supply Ground.
相关PDF资料 |
PDF描述 |
|---|---|
| MT4JSF6464HIY-80BXX | 64M X 64 DDR DRAM MODULE, ZMA204 |
| MT4JSF6464HY-1G4XX | 64M X 64 DDR DRAM MODULE, ZMA204 |
| MT4LC16M4A7DJ-6S | 16M X 4 FAST PAGE DRAM, 60 ns, PDSO32 |
| MT58L128L36P1T-5 | 128K X 36 CACHE SRAM, 2.8 ns, PQFP100 |
| MT58L512Y36FT-8.5 | 512K X 36 CACHE SRAM, 8.5 ns, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LCM32B2P | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SDR SDRAM MT48LC2M32B2 a?? 512K x 32 x 4 Banks |
| MT48NN | 功能描述:插线板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
| MT48NNX | 功能描述:插线板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
| MT48NS | 功能描述:插线板 1 RU PANEL 48 LF JA RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
| MT48NSX | 功能描述:插线板 1/4" LF SLDR BAY 1RU, 2X24, NORM STR RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
发布紧急采购，3分钟左右您将得到回复。