- 您现在的位置：买卖IC网 > PDF目录296642 > MT48LC8M8A2TG-8EL:GIT 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 PDF资料下载
参数资料
| 型号： | MT48LC8M8A2TG-8EL:GIT |
| 元件分类： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 19/55页 |
| 文件大小： | 1454K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页
26
64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
Figure 26
WRITE With Auto Precharge Interrupted by a READ
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out appear-
ing CAS latency later. The PRECHARGE to bank n will
begin after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
4. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a WRITE
on bank n when registered. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
the WRITE to bank m is registered. The last valid data
WRITE to bank n will be data registered one clock prior
to a WRITE to bank m (Figure 27).
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK n
NOP
DIN
d + 1
DIN
d
DIN
a + 1
DIN
a + 2
DIN
a
DIN
d + 2
DIN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
NOP
NOTE: 1. DQM is LOW.
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
WRITE with Burst of 4
Write-Back
WR - BANK n
tRP - BANK n
t WR - BANK m
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK n
NOP
DIN
a + 1
DIN
a
NOP
T7
BANK n
BANK m
ADDRESS
NOTE: 1. DQM is LOW.
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
READ with Burst of 4
t
tRP - BANK m
DOUT
d
DOUT
d + 1
CAS Latency = 3 (BANK m)
RP - BANK n
WR - BANK n
TRANSITIONING DATA
相关PDF资料 |
PDF描述 |
|---|---|
| MT4JSF6464HIY-80BXX | 64M X 64 DDR DRAM MODULE, ZMA204 |
| MT4JSF6464HY-1G4XX | 64M X 64 DDR DRAM MODULE, ZMA204 |
| MT4LC16M4A7DJ-6S | 16M X 4 FAST PAGE DRAM, 60 ns, PDSO32 |
| MT58L128L36P1T-5 | 128K X 36 CACHE SRAM, 2.8 ns, PQFP100 |
| MT58L512Y36FT-8.5 | 512K X 36 CACHE SRAM, 8.5 ns, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LCM32B2P | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SDR SDRAM MT48LC2M32B2 a?? 512K x 32 x 4 Banks |
| MT48NN | 功能描述:插线板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
| MT48NNX | 功能描述:插线板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
| MT48NS | 功能描述:插线板 1 RU PANEL 48 LF JA RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
| MT48NSX | 功能描述:插线板 1/4" LF SLDR BAY 1RU, 2X24, NORM STR RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
发布紧急采购，3分钟左右您将得到回复。