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参数资料
| 型号： | MX10EXAUI |
| 厂商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, LQFP-44 |
| 文件页数： | 15/55页 |
| 文件大小： | 476K |
| 代理商： | MX10EXAUI |
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P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
XA TIMER/COUNTERS
The XA has two standard 16-bit enhanced Timer/Counters:
Timer 0 and Timer 1.Additionally, it has a third 16-bit Up/
Down timer/counter, T2. A central timing generator in the
XA core provides the time-base for all XA Timers and
Counters. The timer/event counters can perform the fol-
lowing functions:
- Measure time intervals and pulse duration
- Count external events
- Generate interrupt requests
- Generate PWM or timed output waveforms
All of the timer/counters (Timer 0, Timer 1 and Timer 2)
can be independently programmed to operate either as
timers or event counters via the C/T bit in the TnCON
register. All timers count up unless otherwise stated.
These timers may be dynamically read during program
execution.
The base clock rate of all of the timers is user program-
mable. This applies to timers T0, T1, and T2 when run-
ning in timer mode (as opposed to counter mode), and
the watchdog timer. The clock driving the timers is called
TCLK and is determined by the setting of two bits (PT1,
PT0) in the System Configuration Register (SCR). The
frequency of TCLK may be selected to be the oscillator
input divided by 4 (Osc/4), the oscillator input divided by
16 (Osc/16), or the oscillator input divided by 64 (Osc/
64). This gives a range of possibilities for the XA timer
functions, including baud rate generation, Timer 2 cap-
ture. Note that this single rate setting applies to all of the
timers.
When timers T0, T1, or T2 are used in the counter mode,
the register will increment whenever a falling edge (high
to low transition) is detected on the external input pin
corresponding to the timer clock. These inputs are
sampled once every 2 oscillator cycles, so it can take
as many as 4 oscillator cycles to detect a transition.
Thus the maximum count rate that can be supported is
Osc/4. The duty cycle of the timer clock inputs is not
important, but any high or low state on the timer clock
input pins must be present for 2 oscillator cycles before
it is guaranteed to be “seen” by the timer logic.
Timer 0 and Timer 1
The “Timer” or “Counter” function is selected by control
bits C/T in the special function register TMOD. These
two Timer/Counters have four operating modes, which
are selected by bit-pairs (Ml, M0) in the TMOD register.
Timer modes 1, 2, and 3 in XA are kept identical to the
80C51 timer modes for code compatibility. Only the mode
0 is replaced in the XA by a more powerful 16-bit auto-
reload mode. This will give the XA timers a much larger
range when used as time bases.
The recommended Ml, M0 settings for the different modes
are shown in Figure 6.
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