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参数资料
| 型号： | MX10EXAUI |
| 厂商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, LQFP-44 |
| 文件页数： | 39/55页 |
| 文件大小： | 476K |
| 代理商： | MX10EXAUI |
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44
P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
AC ELECTRICAL CHARACERISTICS (5V)
VDD = 4.5V to 5.5V; Tamb = 0 to +70
°C for commercial - 40OC to +85OC for Industrial
SYMBOL FIGURE
PARAMETER
VARIABLE CLOCK
UNIT
MIN
MAX
External Clock
f
C
26
Oscillator frequency
0
30
MHz
t
C
26
Clock period and CPU timing cycle
1/ f
C
ns
t
CHCX
26
Clock high time
t
C * 0.5
7
ns
t
CLCX
26
Clock low time
t
C * 0.4
7
ns
t
CLCH
26
Clock rise time
5
ns
t
CHCL
26
Clock fall time
5
ns
Address Cycle
t
CRAR
25
Delay from clock rising edge to ALE rising edge
5
46
ns
t
LHLL
20
ALE pulse width (programmable)
(V1 * t
C)-6
ns
t
AVLL
20
Address valid to ALE de-asserted (set-up)
(V1 * t
C)-12
ns
t
LLAX
20
Address hold after ALE de-asserted
(t
C/2)-10
ns
Code Read Cycle
t
PLPH
20
PSEN pulse width
(V2 * t
C )-10
ns
t
LLPL
20
ALE de-asserted to PSEN asserted
(t
C/2)-7
ns
t
AVIVA
20
Address valid to instruction valid, ALE cycle
(V3 * t
C)-36
ns
(access time)
t
AVIVB
21
Address valid to instruction valid, non-ALE cycle
(V4 * t
C)-29
ns
(access time)
t
CPLIV
20
PSEN asserted to instruction valid
(V2 * t
C)-29
ns
(enable time)
t
PXIX
20
Instruction hold after PSEN de-asserted
0
ns
t
PXIZ
20
Bus 3-State after PSEN de-asserted
t
C - 8
ns
(disable time)
t
IXUA
20
Hold time of unlatched part of address after
0
ns
instruction latched
Data Read Cycle
t
RLRH
22
RD pulse width
(V7 * t
C )-10
ns
t
LLRL
22
ALE de-asserted to RD asserted
(t
C/2)-7
ns
t
AVDVA
22
Address valid to data input valid, ALE cycle
(V6 * t
C)-36
ns
(access time)
t
AVDVB
23
Address valid to data input valid, non-ALE cycle
(V5 * t
C)-29
ns
(access time)
t
RLDV
22
RD low to valid data in, enable time
(V7 * t
C)-29
ns
t
RHDX
22
Data hold time after RD de-asserted
0
ns
t
RHDZ
22
Bus 3-State after RD de-asserted (disable time)
t
C-8
ns
t
DXUA
22
Hold time of unlatched part of address after
0
ns
data latched
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