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参数资料
| 型号： | MX10EXAUI |
| 厂商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, LQFP-44 |
| 文件页数： | 35/55页 |
| 文件大小： | 476K |
| 代理商： | MX10EXAUI |
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P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
RESET OPTIONS
The EA pin is sampled on the rising edge of the RST
pulse, and determines whether the device is to begin
execution from internal or external code memory. EA
pulled high configures the XA in single-chip mode. If EA
is driven low, the device enters ROMless mode. After
Reset is released, the EA/WAIT pin becomes a bus wait
signal for external bus transactions.
The BUSW/P3.5 pin is weakly pulled high while reset is
asserted, allowing simple biasing of the pin with a resis-
tor to ground to select the altermate bus width. If the
BUSW pin is not driven at reset, the weak pullup will
causes 1 to be loaded for the bus width, giving a 16-bit
external bus. BUSW may be pulled low with a 2.7K or
smaller value resistor, giving an 8-bit external bus. The
bus width setting from the BUSW pin may be overridden
by software once the user program is running.
Both EA and BUSW must be held for three oscillator
clock times after reset is deasserted to guarantee that
their values are latched correctly.
POWER REDUCTION MODES
The XA supports Idle and Power Down modes of power
reduction. The idle mode leaves some peripherals run-
ning to allow them to wake up the processor when an
interrupt is generated. The power down mode stops the
oscillator in order to minimize power. The processor can
be made to exit power down mode via reset or one of the
external interrupt inputs. In order to use an external inter-
rupt to re-activate the XA while in power down mode, the
external interrupt must be enabled and be configured to
level sensitive mode. In power down mode, the power
supply voltage may be reduced to the RAM keep-alive
voltage (2V), retaining the RAM, register, and SFR val-
ues at the point where the power down mode was en-
tered.
INTERRUPTS
The XA supports 38 vectored interrupt sources. These
include 9 maskable event interrupts, 7 exception inter-
rupts, 16 trap interrupts, and 7 software interrupts. The
maskable interrupts each have 8 priority levels and may
be globally and/or individually enabled or disabled.
The XA defines tour types of interrupts:
Exception Interrupts - These are system level errors
and other very important occurrences which include stack
overflow, divid-by-0, and reset.
Event Interrupts - These are peripheral interrupts from
devices such as UARTs, timers, and external interrupt
inputs.
Software Interrupts - These are equivalent of hard-
ware interrupt, but are requested only under software
control.
Trap Interrupts - These are TRAP instructions, gener-
ally used to call system services in a multi-tasking sys-
tem.
Exception interrupts, software interrupts, and trap inter-
rupts are generally standard for XA derivatives and are
detailed in the XA User Guide. Event interrupts tend to
be different on different XA derivatives.
The XA supports a total of 9 maskable event interrupt
sources (for the various XA peripherals), seven software
interrupts, 5 exception interrupts (plus reset), and 16 traps.
The maskable event interrupts share a global interrupt
disable bit (the EA bit in the IEL register) and each also
has a separate individual interrupt enable bit (in the IEL
or IEH registers). Only three bits of the IPA register val-
ues are used on the XA. Each event interrupt can be set
to occur at one of 8 priority levels via bits in the Interrupt
Priority (IP) registers, IPA0 through IPA5. The value 0 in
the IPA field gives the interrupt priority 0, in effect dis-
abling the interrupt. A value of 1 gives the interrupt a
priority of 9, the value 2 gives priority 10, etc. The result
is the same as if all four bits were used and the top bit
set for all values except 0.
The complete interrupt vector list for the XA, including
all 4 interrupt types, is shown in the following tables. The
tables include the address of the vector for each inter-
rupt, the related priority register bits (if any), and the ar-
bitration ranking for that interrupt source. The arbitration
ranking determines the order in which interrupts are pro-
cessed if more than one interrupt of the same priority
occurs simultaneously.
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