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参数资料
| 型号： | MX10EXAUI |
| 厂商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, LQFP-44 |
| 文件页数： | 29/55页 |
| 文件大小： | 476K |
| 代理商： | MX10EXAUI |
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P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
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--
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FEn
BRn
MSB
LSB
OEn STINTn
Bit Addressable
Reset Value:00H
S1STAT 425
SnSTATAddress: S0STAT 421
BIT
SYMBOL
FUNCTION
SnSTAT.3
FEn
Framing Error flag is set when the receiver fails to see a valid STOP bit at the end
of the frame. Cleared by software.
SnSTAT.2
BRn
Break Detect flag is set if a character is received with all bits (including STOP bit)
being logic ‘0’. Thus it gives a “Start of Break Detect” on bit 8 for Mode 1 and bit
9 for Modes 2 and 3. The break detect feature operates independently of the UARTs
and provides the START of Break Detect status bit that a user program may poll.
Cleared by software.
SnSTAT.1
OEn
Overrun Error flag is set if a new character is received in the receiver buffer while it
is still full (before the software has read the previous character from the buffer), i.e.,
when bit 8 of a new byte is received while RI in SnCON is still set. Cleared by
software.
SnSTAT.0
STINTn
This flag must be set to enable any of the above status flags to generate a receive
interrupt (Rln). The only way it can be cleared is by a software write to this register.
Figure 15. Serial Port Extended Status (SnSTAT) Register
(See also Figure 17 regarding Framing Error flag)
INTERRUPT SCHEME
There are separate interrupt vectors for each UART ’ s
transmit and receive functions.
Table 6. Vector Locations for UARTS in XA
Vector Address Interrupt Source
Arbitration
A0H - A3H
UART 0 Receiver
7
A4H - A7H
UART 0 Transmitter 8
A8H - ABH
UART I Receiver
9
ACH-AFH
UARTI Transmitter
10
NOTE:
The transmit and receive vectors could contain the same
ISR address to work like a 8051 interrupt scheme
Error Handling, Status Rags and Break Detect
The UARTs in XA has the following error flags; see Fig-
ure 15.
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiproces-
sor communications. in these modes, 9 data bits are
received. The 9th one goes into RB8. Then comes a stop
bit. The port can be programmed such that when the
stop bit is received, the serial port interrupt will be acti-
vated only if RB8 = 1. This feature is enabled by setting
bit SM2 in SCON. A way to use this feature in multipro-
cessor systems is as follows:
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an ad-
dress byte which identifies the target slave. An address
byte differs from a data byte in that the 9th bit is 1 in an
address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can
examine the received byte and see if it is being addressed.
The addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will be coming. The slaves
that weren’t being addressed leave their SM2s set and
go on about their business, ignoring the coming data
bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be
used to check the validity of the stop bit although this is
better done with the Framing Error (FE) flag. In a Mode 1
reception, if SM2 = 1, the receive interrupt will not be
activated unless a valid stop bit is received.
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