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参数资料
| 型号： | NCP1608BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | IC PFC CTLR/PRECONVERTER 8-SOIC |
| 标准包装： | 1 |
| 模式： | 临界传导（CRM） |
| 电流 - 启动： | 24µA |
| 电源电压： | 10.2 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 标准包装 |
| 其它名称： | NCP1608BDR2GOSDKR |
NCP1608
V out
R out1 +
R out1 @ R FB
R out2 +
V out
V REF
V out + V REF @ R out1 @
R out2 ) R FB
R out2 @ R FB
A resistor divider (R out1 and R out2 ) scales down the boost
output voltage (V out ) and is connected to the FB pin. If the
output voltage is less than the target output voltage, then
V FB is less than V REF and the EA increases the control
voltage (V Control ). This increases the on time of the driver,
which increases the power delivered to the output. The
increase in delivered power causes V out to increase until the
target output voltage is achieved. Alternatively, if V out is
greater than the target output voltage, then V Control
decreases to cause the on time to decrease until V out
decreases to the target output voltage. This cause and effect
regulates V out so that the scaled down V out that is applied
to FB through R out1 and R out2 is equal to V REF . The
presence of R FB (4.6 M W typical value) for FPP is included
in the divider network calculation.
The output voltage is set using Equation 2:
) 1 (eq. 2)
The divider network bias current is selected to optimize
the tradeoff of noise immunity and power dissipation. R out1
is calculated using the bias current and output voltage using
(eq. 3)
I bias(out)
Where I bias(out) is the output divider network bias current.
R out2 is dependent on V out , R out1 , and R FB .
R out2 is calculated using Equation 4:
(eq. 4)
R FB @ * 1 * R out1
The PFC stage consumes a sinusoidal current from a
sinusoidal line voltage. The converter provides the load
with a power that matches the average demand only. The
output capacitor (C bulk ) compensates for the difference
between the delivered power and the power consumed by
the load. When the power delivered to the load is less than
the power consumed by the load, C bulk discharges. When
the delivered power is greater than the power consumed by
the load, C bulk charges to store the excess energy. The
situation is depicted in Figure 30.
Equation 3:
Iac
Vac
P in
P out
V out
Figure 30. Output Voltage Ripple for a Constant Output Power
C COMP +
2 @ p @ f CROSS
V Ct(off) + V Control ? Ct (offset) + (eq. 6)
Due to the charging/discharging of C bulk , V out contains
a ripple at a frequency of either 100 Hz (for a 50 Hz line
frequency in Europe) or 120 Hz (for a 60 Hz line frequency
in the USA). The V out ripple is attenuated by the regulation
loop to ensure V Control is constant during the ac line cycle
for the proper shaping of the line current. To ensure V Control
is constant during the ac line cycle, the loop bandwidth is
typically set below 20 Hz. A type 1 compensation network
consists of a capacitor (C COMP ) connected between the
Control and ground pins (see Figure 1). The capacitor value
that sets the loop bandwidth is calculated using Equation 5:
gm
(eq. 5)
Where f CROSS is the crossover frequency and gm is the
error amplifier transconductance. The crossover frequency
is set below 20 Hz.
On Time Sequence
The switching pattern consists of constant on times and
variable off times for a given rms input voltage and output
load. The NCP1608 controls the on time with the capacitor
connected to the Ct pin. A current source charges the Ct
capacitor to a voltage derived from the Control pin voltage
(V Ct(off) ). V Ct(off) is calculated using Equation 6:
2 @ P out @ L @ I charge
h @ Vac 2 @ Ct
When V Ct(off) is reached, the drive turns off (Figure 31).
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