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参数资料
| 型号： | NCP1608BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 22/24页 |
| 文件大小： | 0K |
| 描述： | IC PFC CTLR/PRECONVERTER 8-SOIC |
| 标准包装： | 1 |
| 模式： | 临界传导（CRM） |
| 电流 - 启动： | 24µA |
| 电源电压： | 10.2 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 标准包装 |
| 其它名称： | NCP1608BDR2GOSDKR |
NCP1608
BOOST DESIGN EQUATIONS Components are identified in Figure 1
Input rms Current
Inductor Peak Current
Iac +
I L(peak) +
P out
h @ Vac
2 @ 2 @ P out
h @ Vac
h (the efficiency of only the PFC
stage) is generally in the range of 90
? 95%. Vac is the rms ac line input
voltage.
The maximum inductor peak current
occurs at the minimum line input
voltage and maximum output power.
V out
Vac 2 @ * Vac @ h
Inductor Value
L v
2
2 @ V out @ P out @ f SW(MIN)
f SW(MIN) is the minimum desired
switching frequency. The maximum L
is calculated at both the minimum
line input voltage and maximum line
input voltage.
On Time
t on +
2 @ L @ P out
h @ Vac 2
The maximum on time occurs at the
minimum line input voltage and max-
imum output power.
Off Time
t off +
t on
V out
Vac @ sin q @ 2
* 1
The off time is a maximum at the
peak of the ac line voltage and ap-
proaches zero at the ac line zero
crossings. Theta ( q ) represents the
angle of the ac line voltage.
Switching Frequency
f SW +
Vac 2 @ h
2 @ L @ P out
@
1 *
Vac @ |sin q | @ 2
V out
On Time Capacitor
Ct w
2 @ P out @ L MAX @ I charge
h @ Vac LL 2 @ V Ct(MAX)
Where Vac LL is the minimum line in-
put voltage and L MAX is the maxim-
um inductor value. I charge and
V Ct(MAX) are shown in the specifica-
tion table.
Inductor Turns to ZCD
Turns Ratio
N B : N ZCD v
V out * 2 @ Vac HL
V ZCD(ARM)
Where Vac HL is the maximum line
input voltage. V ZCD(ARM) is shown in
the specification table.
Resistor from ZCD
Winding to the ZCD pin
R ZCD w
2 @ Vac HL
I ZCD(MAX) @ (N B : N ZCD )
Where I ZCD(MAX) is maximum rated
current for the ZCD pin (10 mA).
R out1 +
Output Voltage and Output
Divider
V out + V REF @ R out1 @
V out
I bias(out)
R out2 ) R FB
R out2 @ R FB
) 1
Where V REF is the internal reference
voltage and R FB is the pull ? down
resistor used for FPP. V REF and R FB
are shown in the specification table.
I bias(out) is the bias current of the out-
put voltage divider.
* 1 * R out1
R out2 +
R FB @
R out1 @ R FB
V out
V REF
@ V REF @ R out1 @ out2
Output Voltage OVP
Detection and Recovery
V out(OVP) +
V OVP
V REF
R ) R FB
R out2 @ R FB
) 1
V OVP /V REF and V OVP(HYS) are
shown in the specification table.
V out(OVPL) +
V OVP
V REF
@ V REF ? V OVP(HYS) @ R out1 @
R out2 ) R FB
R out2 @ R FB
) 1
C bulk w
Output Voltage Ripple and
Output Capacitor Value
V ripple(peak ? peak) t 2 @ V out(OVP) * V out
P out
2 @ p @ V ripple(peak ? peak) @ f line @ V out
Where f line is the ac line frequency
and V ripple(peak ? peak) is the peak ? to ?
peak output voltage ripple. Use f line =
47 Hz for universal input worst case.
Output Capacitor rms
Current
I C(RMS) +
2 @ 32 @ P out 2
9 @ p @ Vac @ V out @ h 2
* I load(RMS) 2
Where I load(RMS) is the rms load cur-
rent.
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