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| 型号： | NCP1608BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/24页 |
| 文件大小： | 0K |
| 描述： | IC PFC CTLR/PRECONVERTER 8-SOIC |
| 标准包装： | 1 |
| 模式： | 临界传导（CRM） |
| 电流 - 启动： | 24µA |
| 电源电压： | 10.2 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 标准包装 |
| 其它名称： | NCP1608BDR2GOSDKR |
NCP1608
During the delay caused by R ZCD and the ZCD pin capacitance, the equivalent drain capacitance (C EQ(drain) ) discharges
through the path shown in Figure 35.
L
I L
D
V out
AC Line
I in
EMI
Filter
+
C in
C EQ(drain)
+
C bulk
Figure 35. Equivalent Drain Capacitance Discharge Path
C EQ(drain) is the combined parasitic capacitances of the
MOSFET, the diode, and the inductor. C in is charged by the
energy discharged by C EQ(drain) . The charging of C in
reverse biases the bridge rectifier and causes the input
stored in the inductor (L) to be reduced. The result is that
V ZCD does not exceed V ZCD(ARM) and the drive remains off
until t start expires. This sequence results in pulse skipping
and reduced power factor.
current (I in ) to decrease to zero. The zero input current
causes THD to increase. To reduce THD, the ratio (t z / T SW )
is minimized, where t Z is the period from when I L = 0 A to
when the drive turns on. The ratio (t z / T SW ) is inversely
proportional to the square root of L.
During startup, there is no energy in the ZCD winding
and no voltage signal to activate the ZCD comparators.
This means that the drive never turns on. To enable the PFC
stage to start under these conditions, an internal watchdog
V Control
Ct (offset)
V Ct
V Ct(off)
Noise Induced Voltage Spike
Low V Control Voltage
V Control ? Ct (offset)
timer (t start ) is integrated into the controller. This timer
turns the drive on if the drive has been off for more than
165 m s (typical value). This feature is deactivated during a
fault mode (OVP or UVP), and reactivated when the fault
is removed.
DRV
Low V Ct(off) Voltage
Wide Control Range
The Ct charging threshold (V Ct(off) ) decreases as the
output power is decreased from the maximum output
power to the minimum output power in the application. In
V ZCD
V ZCD(ARM)
V ZCD(TRIG)
V ZCD(ARM)
is Not Exceeded
high power applications (>150 W), V Control is reduced to
a low voltage at a large output power and Ct (offset) remains
constant. The result is that V Ct(off) is reduced to a low
voltage at a large output power. The low V Control and
V Ct(off) voltages are susceptible to noise. The large output
power combined with the low V Control and V Ct(off) increase
the probability of noise interfering with the control signals
V CL(NEG)
t on(loop)
t on
DRV Remains Off
t start
0V
and on time duration (Figures 36 and 37). The noise induces
voltage spikes on the Control pin and Ct pin that reduces the
drive on time from the on time determined by the feedback
Figure 36. Control Pin Noise Induced On Time
Reduction and Pulse Skipping
loop (t on(loop) ). The reduced on time causes the energy
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