参数资料
型号: NCP4208MNR2G
厂商: ON Semiconductor
文件页数: 10/30页
文件大小: 0K
描述: IC CTLR 8PH VR11.1 PMBUS 48-QFN
标准包装: 2,500
应用: 控制器,Intel VR11.1
输入电压: 4.7 V ~ 5.75 V
输出数: 8
输出电压: 0.16 V ~ 5 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
NCP4208
Theory of Operation
The NCP4208 is an 8 ? phase VR11 controller; it combines
a multi ? mode, fixed frequency PWM control with
multi ? phase logic outputs for use in multi ? phase
synchronous buck CPU core supply power converters. In
addition, the NCP4208 incorporates a serial interface to
allow the programming of key system performance
specifications and read back CPU data such as voltage,
current and power. Multiphase operation is important for
producing the high currents and low voltages demanded by
today’s microprocessors. Handling the high currents in a
single ? phase converter would place high thermal demands
on the components in the system such as the inductors and
MOSFETs.
Startup Sequence
The NCP4208 follows the VR11 startup sequence shown
in Figure 7. After both the EN and UVLO conditions are
met, a programmable internal timer goes through one cycle
(TD2 in Figure 7) starts. The SS circuit uses the internal VID
DAC to increase the output voltage in 6.25 mV steps up to
the 1.1 V boot voltage.
Once the SS circuit has reached the boot voltage, the boot
voltage delay time (TD3) is started. The end of the boot
voltage delay time signals the beginning of the second
soft ? start time (TD4). The SS voltage changes from the boot
voltage to the programmed VID DAC voltage (either higher
or lower) using 6.25 mV steps.
The soft ? start slew rate is programmed using Bits <2:0>
of the Ton_Rise (0xD5) command code. Table 1. Soft ? Start
Codes provides the soft ? start values. Figure 8 shows typical
startup waveforms for the NCP4208.
Table 1. Soft ? Start Codes
Code Soft ? Start (V/msec)
000 0.3
001 0.3
TD1. This delay cycle is programmed using Delay
Command, default delay = 2 ms). The first eight clock
cycles of TD2 are blanked from the PWM outputs and used
for phase detection as explained in the following section.
Then the programmable internal soft ? start ramp is enabled
(TD2) and the output comes up to the boot voltage of 1.1 V.
The boot hold time is also set by the Delay Command. This
second delay cycle is called TD3. During TD3 the processor
VID pins settle to the required VID code. When TD3 is over,
the NCP4208 reads the VID inputs and soft starts either up
or down to the final VID voltage (TD4). After TD4 has been
completed and the PWRGD masking time (equal to VID
OTF masking) is finished, a third cycle of the internal timer
sets the PWRGD blanking (TD5).
The internal delay and soft ? start times are programmable
using the serial interface and the Delay Command and
Soft ? Start Command.
UVLO
THRESHOLD
5.0 V
SUPPLY
010
011
100
101
110
111
0.5 = default
0.7
0.9
1.1
1.3
1.5
VTT I/O
(NCP4208 EN)
VCC_CORE
VR READY
(ADP4000 PWRGD)
0.85 V
TD1
TD2
TD3
V BOOT
(1.1 V)
V VID
TD4
Figure 8. Typical Startup Waveforms
Channel 1: CSREF, Channel 2: EN, Channel 3: PWM1
Phase Detection
CPU
VID INPUTS
VID INVALID
50 m s
TD5
VID VALID
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the NCP4208 operates
Figure 7. System Startup Sequence for VR11
Soft ? Start
The Soft ? Start slope for the output voltage is set by an
internal timer. The default value is 0.5 V/msec, which can be
programmed through the I 2 C interface. After TD1 and the
phase detection cycle have been completed, the SS time
as an 8 ? phase PWM controller.
To operate as a 7 ? phase controller connect PWM8 to V CC .
To operate as a 6 ? phase controller, connect PWM7 and
PWM8 to V CC . To operate as a 5 ? phase controller connect
PWM6, PWM7 and PWM8 to V CC . To operate as a 4 ? phase
controller, connect PWM5, PWM6, PWM7 and PWM8 to
V CC . To operate as a 3 ? phase controller, connect PWM4,
PWM5, PWM6, PWM7 and PWM8 to V CC . To operate as
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