参数资料
| 型号： | NCP4208MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/30页 |
| 文件大小： | 0K |
| 描述： | IC CTLR 8PH VR11.1 PMBUS 48-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 4.7 V ~ 5.75 V |
| 输出数： | 8 |
| 输出电压： | 0.16 V ~ 5 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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NCP4208
startup sequence. Also, it is used for timing the current limit
latchoff as explained in the Current Limit section. The
current limit timer is set to 4 times the delay timer.
The delay timer is programmed using Bits <2:0> of the
Ton Delay command (0xD4). The delay can be programmed
between 0.5 msec and 4 msec. Table 6 provides the
programmable delay values.
Table 6. Delay Codes
This secondary current limit limits controls of the internal
COMP voltage to the PWM comparators to 1.5 V. This
limits the voltage drop across the low ? side MOSFETs
through the current balance circuitry. Typical overcurrent
latchoff waveforms are shown in Figure 9.
Code
000
001
010
011
100
101
110
111
Delay (msec)
0.5
1
1.5
2 = default
2.5
3
3.5
4
Current Limit, Short ? Circuit and Latchoff Protection
The NCP4208 compares a programmable current limit set
point to the voltage from the output of the current sense
amplifier. The level of current limit is set with the resistor
from the ILIMFS pin to CSCOMP, and can be adjusted using
the I 2 C interface.
The current limit threshold can be modified from the
resistor programmed value by using the I 2 C interface using
Bits <4:0> of the Current Limit Threshold command
(0xE2). The limit is programmable between 50% of the
external limit and 146.7% of the external limit. The
resolution is 3.3%. The current limit threshold can be
modified from the resistor programmed value by using the
serial interface.
If the limit is reached and TD5 has completed, an internal
latchoff delay time will start, and the controller will shut
down if the fault is not removed. This delay is four times
longer than the delay time during the startup sequence. The
current limit delay time only starts after the TD5 has
completed. If there is a current limit during startup, the
NCP4208 will go through TD1 to TD5, and then start the
latchoff time. As the controller continues to cycle the phases
during the latchoff delay time, if the short is removed before
the timer is complete, the controller can return to normal
operation.
The latchoff function can be reset by either removing and
reapplying the supply voltage to the NCP4208, or by
toggling the EN pin low for a short time.
The OCP latchoff function can be disabled by using the
I 2 C interface. Setting the CLIM_EN bit (bit 1) of the VR
Config 1A (0xD2) and VR Config 1B (0xD3) registers to 0
disables the current limit latchoff function. The NCP4208
can continue to operate in current limit indefinitely.
During startup when the output voltage is below 200 mV,
a secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground.
Figure 9. Overcurrent Latchoff Waveforms
Channel 1: CSREF, Channel 2: COMP,
Channel 3: PWM1
An inherent per phase current limit protects individual
phases if one or more phases stops functioning because of a
faulty component. This limit is based on the maximum
normal mode COMP voltage.
Power Good Monitoring
The power good comparator monitors the output voltage
via the CSREF pin. The PWRGD pin is an open ? drain
output whose high level (when connected to a pullup
resistor) indicates that the output voltage is within the
nominal limits specified in the specifications above based on
the VID voltage setting. PWRGD goes low if the output
voltage is outside of this specified range, if the VID DAC
inputs are in no CPU mode, or whenever the EN pin is pulled
low. PWRGD is blanked during a DVID event for a period
of 100 m s to prevent false signals during the time the output
is changing.
The PWRGD circuitry also incorporates an initial turn ? on
delay time (TD5). Prior to the SS voltage reaching the
programmed VID DAC voltage and the PWRGD masking
time finishing, the PWRGD pin is held low. Once the SS
circuit reaches the programmed DAC voltage, the internal
timer operates.
The value for the PWRGD high limit and low limit can be
programmed using the serial interface.
Power State Indicator
The PSI pin is an input used to determine the operating
state of the load. If this input is pulled low, the load is in a low
power state and the controller asserts the ODN pin low,
which can be used to disable phases and maintain better
efficiency at lighter loads.
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