参数资料
| 型号： | NCP4208MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 27/30页 |
| 文件大小： | 0K |
| 描述： | IC CTLR 8PH VR11.1 PMBUS 48-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 4.7 V ~ 5.75 V |
| 输出数： | 8 |
| 输出电压： | 0.16 V ~ 5 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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NCP4208
Cmd
Code
R/W
Default
Description
#
Bytes
Comment
0xD2
R/W
0x72
VR Config. 1A
1
Bit
Name
Description
6:4
3
2
1
0
Phase
Enable Bits
VID_EN
LOOP_EN
CLIM_EN
Res
000 = Phase 1
001 = Phase 2
010 = Phase 3
011 = Phase 4
100 = Phase 5
101 = Phase 6
110 = Phase 7
111 = Phase 8
When the VID_EN bit is set to 1, the VID
code in the VOUT_COMMAND register sets
the output voltage. When VID_EN is set to 0,
the output voltage follows the VID input pins.
When the LOOP_EN bit is set to 1 in both
registers, the control loop test function is
enabled. This allows measurement of the
control loop AC gain and phase response
with appropriate instrumentation. The control
loop signal insertion pin is I MON . The control
loop output pin is COMP.
When CLIM_EN is set to 1, the current limit
time out latchoff functions normally. When
this bit is set to 0 in both registers, the
current limit latchoff is disabled. In this state,
the part can be in current limit indefinitely.
Reserved for future use.
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xDD
0xDE
R/W
R/W
R/W
R/W
R
R
R/W
R/W
0x72
0x03
0x02
0x01
0x00
0x00
0x00
0x10
VR Config. 1B
Ton Delay
Ton Rise
Ton Transition
V MON Voltage
EN/VTT Voltage
VOUT_CAL
Loadline Calibration
1
1
1
1
2
2
1
1
This register is for security reasons. It has the same format as
register 0xD2. Bits need to be set in both registers for the function
to take effect.
This is a 16 bit value that reports back the voltage measured
between FB and FBRTN
This is a 16 bit value that reports back the voltage on the VTT Pin.
Offset Command Code for V OUT , max ± 200 mV
This value sets the internal loadline attenuation DAC calibration
value. The maximum loadline is controlled externally by setting the
gain of the current sense amplifier as explained in the applications
section. This maximum loadline can then be adjusted from 100% to
0% in 30 steps. Each LSB represents a 3.226% change in the load
line.
00000 = No Load Line
10000 = 51.6% of external load line
11111 = 100% of external Loadline
0xDF
R/W
0x00
Loadline Set
1
This value sets the internal loadline attenuation DAC value. The
maximum loadline is controlled externally by setting the gain of the
current sense amplifier as explained in the applications section.
This maximum loadline can then be adjusted from 100% to 0% in
30 steps. Each LSB represents a 3.226% change in the load line.
00000 = No Load Line
10000 = 51.6% of external load line
11111 = 100% of external load Line
0xE0
R/W
0x00
PWRGD Hi Threshold
1
This value sets the PWRGD Hi Threshold and the CROWBAR
Threshold:
Code = 00, PWRGD HI = 300 mV (default)
Code = 01, PWRGD HI = 250 mV
Code = 10, PWRGD HI = 200 mV
Code = 11, PWRGD HI = 150 mV
http://onsemi.com
27
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| NCP4300A | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Operational Amplifier and Voltage Reference |
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| NCP4300AD | 功能描述:运算放大器 - 运放 2.6V Ref. RoHS:否 制造商:STMicroelectronics 通道数量:4 共模抑制比（最小值）:63 dB 输入补偿电压:1 mV 输入偏流（最大值）:10 pA 工作电源电压:2.7 V to 5.5 V 安装风格:SMD/SMT 封装 / 箱体:QFN-16 转换速度:0.89 V/us 关闭:No 输出电流:55 mA 最大工作温度:+ 125 C 封装:Reel |
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