参数资料
| 型号： | NCP4208MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/30页 |
| 文件大小： | 0K |
| 描述： | IC CTLR 8PH VR11.1 PMBUS 48-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 4.7 V ~ 5.75 V |
| 输出数： | 8 |
| 输出电压： | 0.16 V ~ 5 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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NCP4208
a 2 ? phase controller connect PWM3, PWM4, PWM5,
PWM6, PWM7 and PWM8 to V CC . To operate as a 1 ? phase
controller connect PWM2, PWM3, PWM4, PWM5,
PWM6, PWM7 and PWM8 to V CC .
Prior to soft ? start, while EN is low, the PWM8, PWM7,
PWM6, PWM5, PWM4, PWM3 and PWM2 pins sink
approximately 100 m A each. An internal comparator checks
each pin’s voltage vs. a threshold of 3.0 V. If the pin is tied
to V CC , it is above the threshold. Otherwise, an internal
current sink pulls the pin to GND, which is below the
threshold. PWM1 is low during the phase detection interval
that occurs during the first eight clock cycles of TD2. After
this time, if the remaining PWM outputs are not pulled to
V CC , the 100 m A current sink is removed, and they function
as normal PWM outputs. If they are pulled to V CC , the
100 m A current source is removed, and the outputs are put
into a high impedance state.
The PWM outputs are logic ? level devices intended for
driving fast response external gate drivers such as the
ADP3121. Because each phase is monitored independently,
operation approaching 100% duty cycle is possible. In
addition, more than one output can be on at the same time to
allow overlapping phases.
Master Clock Frequency
The clock frequency of the NCP4208 is set with an
external resistor connected from the RT pin to ground. The
frequency follows the graph in Figure 3. To determine the
frequency per phase, the clock is divided by the number of
phases in use. If all phases are in use, divide by 8. If 4 phases
are in use divide by 4.
Output Voltage Differential Sensing
The NCP4208 combines differential sensing with a high
accuracy VID DAC and reference, and a low offset error
amplifier. This maintains a worst ? case specification of
± 9 mV differential sensing error over its full operating
output voltage and temperature range. The output voltage is
sensed between the FB pin and FBRTN pin. FB is connected
through a resistor, R B, to the regulation point, usually the
remote sense pin of the microprocessor. FBRTN is
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a minimal current of 70 m A to allow
accurate remote sensing. The internal error amplifier
compares the output of the DAC to the FB pin to regulate the
method than peak current detection or sampling the current
across a sense element such as the low ? side MOSFET. This
amplifier can be configured several ways, depending on the
objectives of the system, as follows:
? Output inductor DCR sensing without a thermistor for
lowest cost.
? Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor
temperature.
? Sense resistors for highest accuracy measurements.
The positive input of the CSA is connected to the
CSREF pin, which is connected to the average output
voltage. The inputs to the amplifier are summed together
through resistors from the sensing element, such as the
switch node side of the output inductors, to the inverting
input CSSUM. The feedback resistor between CSCOMP
and CSSUM sets the gain of the amplifier and a filter
capacitor is placed in parallel with this resistor. The gain of
the amplifier is programmable by adjusting the feedback
resistor. This difference signal is used internally to offset the
VID DAC for voltage positioning. This different signal can
be adjusted between 50% ? 150% of the external value using
the I 2 C Loadline Calibration (0xDE) and Loadline Set
(0xDF) commands.
The difference between CSREF and CSCOMP is then
used as a differential input for the current limit comparator.
To provide the best accuracy for sensing current, the CSA
is designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors to make it
extremely accurate.
The CPU current can also be monitored over the I 2 C
interface. The current limit and the loadline can be
programmed over I 2 C interface.
Loadline Setting
The Loadline is programmable over the I 2 C on the
NCP4208. It is programmed using the Loadline Calibration
(0xDE) and Loadline Set (0xDF) commands. The Loadline
can be adjusted between 0% and 100% of the external R CSA.
In this example R CSA = 1 m W . R O needs to be 0.8 m W ,
therefore programming the Loadline Calibration + Loadline
Set register to give a combined percentage of 80% will set
the R O to 0.8 m W .
Table 2. Loadline Commands
output voltage.
Output Current Sensing
The NCP4208 provides a dedicated current sense
amplifier (CSA) to monitor the total output current for
proper voltage positioning vs. load current, for the I MON
output and for current limit detection. Sensing the load
current at the output gives the total real time current being
delivered to the load, which is an inherently more accurate
http://onsemi.com
11
Code
0 0000
0 0001
1 0000
1 0001
1 1110
1 1111
Loadline (as a percentage of R CSA )
0%
3.226%
51.6% = default
53.3%
96.7%
100%
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| NCP4300A | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Operational Amplifier and Voltage Reference |
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| NCP4300AD | 功能描述:运算放大器 - 运放 2.6V Ref. RoHS:否 制造商:STMicroelectronics 通道数量:4 共模抑制比（最小值）:63 dB 输入补偿电压:1 mV 输入偏流（最大值）:10 pA 工作电源电压:2.7 V to 5.5 V 安装风格:SMD/SMT 封装 / 箱体:QFN-16 转换速度:0.89 V/us 关闭:No 输出电流:55 mA 最大工作温度:+ 125 C 封装:Reel |
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