参数资料
| 型号： | NCP4208MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/30页 |
| 文件大小： | 0K |
| 描述： | IC CTLR 8PH VR11.1 PMBUS 48-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 4.7 V ~ 5.75 V |
| 输出数： | 8 |
| 输出电压： | 0.16 V ~ 5 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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NCP4208
The sequencing into and out of low power operation is
maintained to minimize output deviations as well as
providing full power load transients immediately after
exiting a low power state. The number of phases switched on
when PSI is asserted is set using Bits 7:6 of the Manufacturer
Config Register 0x03. Table 7 shows which phases are
enabled for each configuration.
Table 7. Configuration and Enabled Phases
action stops once the output voltage falls below the release
threshold of approximately 300 mV.
The value for the crowbar limit follows the programmable
PWRGD high limit.
Turning on the low ? side MOSFETs pulls down the output
as the reverse current builds up in the inductors. If the output
overvoltage is due to a short in the high ? side MOSFET, this
action current limits the input supply or blows its fuse,
protecting the microprocessor from being destroyed.
# Phases
Running
Normally
8
7
6
5
4
3
Code
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
# Phases
Running
During
PSI
1
2
4
4
1
1
1
1
1
2
3
1
1
1
1
1
1
1
1
1
1
1
1
Current
Limit
Divided by:
4
4
2
2
4
4
2
2
4
3
2
2
4
2
2
2
4
2
2
2
3
2
2
Phases
Running
1
1 and 5
1, 3, 5, 7
1, 3, 5, 7
1
1
1
1
1
1 and 4
1, 3, 5
1, 3, 5
1
1
1
1
1
1
1
1
1
1
1
Output Enable and UVLO
For the NCP4208 to begin switching, the input supply
current to the controller must be higher than the UVLO
threshold and the EN pin must be higher than its 0.8 V
threshold. This initiates a system startup sequence. If either
UVLO or EN is less than their respective thresholds, the
NCP4208 is disabled. This holds the PWM outputs at
ground and forces PWRGD, ODN and OD1 signals low.
In the application circuit (see Figure 2), the OD1 pin
should be connected to the OD inputs of the external drivers
for the phases that are always on. The ODN pin should be
connected to the OD inputs of the external drivers on the
phases that are shut down during low power operation.
Grounding the driver OD inputs disables the drivers such
that both DRVH and DRVL are grounded. This feature is
important in preventing the discharge of the output
capacitors when the controller is shut off. If the driver
outputs are not disabled, a negative voltage can be generated
during output due to the high current discharge of the output
capacitors through the inductors.
The NCP4208 uses a shunt to generate 5.0 V from the
12 V supply range. A trade-off can be made between the
power dissipated in the shunt resistor and the UVLO
threshold. Figure 10 shows the typical resistor value needed
to realize certain UVLO voltages. It also gives the maximum
power dissipated in the shunt resistor for these UVLO
voltages.
400 0.325
2
1
11
00
01
10
11
00
01
10
11
1
1
1
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
350
300
250
200
150
0.3
0.275
0.25
0.225
0.2
0.175
8
9
10
11
12
13
14
15
16
Output Crowbar
As part of the protection for the load and output
components of the supply, the PWM outputs are driven low
(turning on the low ? side MOSFETs) when the output
ICC (UVLO)
Rshunt
Pshunt
2 ? 0603 Limit
2 ? 0805 Limit
voltage exceeds the upper crowbar threshold. This crowbar
Figure 10. Typical Shunt Resistor Value and Power
Dissipation for Different UVLO Voltage
http://onsemi.com
15
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