参数资料
| 型号： | NCP4208MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/30页 |
| 文件大小： | 0K |
| 描述： | IC CTLR 8PH VR11.1 PMBUS 48-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 4.7 V ~ 5.75 V |
| 输出数： | 8 |
| 输出电压： | 0.16 V ~ 5 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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NCP4208
ELECTRICAL CHARACTERISTICS
V IN = (5.0 V) FBRTN ? GND, for typic al values T A = 25 ° C, for min/max values T A = 0 ° C to 85 ° C; unless otherwise noted. (Notes 1 and 2)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Reference Current
Reference Bias Voltage
Reference Bias Current
R IREF = 121 k W
V IREF
I IREF
1.75
1.8
15
1.85
V
m A
Error Amplifier
Output Voltage Range
V COMP
0
4.4
V
Accuracy
Load Line Positioning Accuracy
Relative to nominal DAC output, referenced
to FBRTN (refer to Figure 4)
In startup
V FB
V FB(BOOT)
? 9.0
1.091
? 77
1.1
? 80
+9.0
1.109
? 83
mV
V
mV
Load Line Range
Load Line Attenuation
Differential Non ? linearity
? 350
0
? 1.0
0
100
+1.0
mV
%
LSB
Input Bias Current
I FB = I IREF
I FB
13.3
15
18.5
m A
Offset Accuracy
VR Offset Register = 111111, VID = 1.0 V
VR Offset Register = 011111, VID = 1.0 V
? 193.75
193.75
mV
FBRTN Current
I FBRTN
100
200
m A
Output Current
Gain Bandwidth Product
Slew Rate
BOOT Voltage Hold Time
FB forced to V OUT ? 3%
COMP = FB
COMP = FB
Internal Timer
I COMP
GBW (ERR)
t BOOT
500
20
25
2.0
m A
MHz
V/ m s
ms
VID Inputs
Input Low Voltage
Input High Voltage
VID(X)
V IL(VID)
V IH(VID)
0.8
0.3
V
Input Current
VID Transition Delay Time
No CPU Detection Turn ? Off Delay
Time
VID code change to FB change
VID code change to PWM going low
I IN(VID)
400
5.0
? 5.0
m A
ns
m s
Oscillator
Frequency Range
f OSC
0.25
9.0
MHz
Frequency Variation
Output Voltage
RAMPADJ Output Voltage
RAMPADJ Input Current Range
T A = 25 ° C, R T = 500 k W , 4 ? phase
T A = 25 ° C, R T = 250 k W , 4 ? phase
T A = 25 ° C, R T = 121 k W , 4 ? phase
RT = 500 k W to GND
RAMPADJ ? FB, V FB = 1.0 V,
IRAMPADJ = ? 150 m A
f PHASE
V RT
V RAMPADJ
I RAMPADJ
170
1.9
? 50
5.0
195
375
750
2.01
225
2.1
+50
60
kHz
V
mV
m A
Current Sense Amplifier
Offset Voltage
Input Bias Current, CSREF
Input Bias Current, CSSUM
Gain Bandwidth Product
Slew Rate
Input Common ? Mode Range
CSSUM ? CSREF (refer to Figure 5)
CSREF = 1.0 V
CSREF = 1.0 V
CSSUM = CSCOMP
C CSCOMP = 10 pF
CSSUM and CSREF
V OS(CSA)
I BIAS(CSREF)
I BIAS(CSSUM)
GBW (CSA)
? 1.0
? 20
? 10
0
10
10
+1.0
+20
+10
3.0
mV
m A
nA
MHz
V/ m s
V
Output Voltage Range
Output Current
Current Limit Latchoff Delay Time
Internal Timer
I CSCOMP
0.05
500
8.0
3.0
V
m A
ms
1. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T J = T A = 25 _ C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
2. Refer to Application Information section.
3. Values based on design and/or characterization.
http://onsemi.com
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