参数资料
型号: NCP4330DR2G
厂商: ON Semiconductor
文件页数: 10/17页
文件大小: 0K
描述: IC DRIVER POST REGULATION 8-SOIC
标准包装: 1
输出隔离: 非隔离
频率范围: 达 400kHz
输入电压: 5.2 V ~ 20 V
输出电压: 0.9 V ~ 23.5 V
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 剪切带 (CT)
其它名称: NCP4330DR2GOSCT
NCP4330
100
75
50
25
free wheeling operation continues (refer to application
schematic).
However, such a situation should occur only during transient
phases. Should this state occur too frequently, an excessive
heating of the Q2 switch could be produced.
70
60
50
40
0
0
0.5
1.0
1.5
2.0
2.5
30
I_ramp (mA)
Figure 25. High ? Side MOSFET Duty Cycle vs. I_ramp
Conditions: Switching Frequency: 400 kHz, Reset Pulse
20
10
Duration: 250 ns, Switching Delay (between LS and HS):
100 ns, Cramp = 100 pF.
0
0
0.1
0.2
0.3 0.4
0.5
0.6
One can note that the duty cycle increases when the
I_ramp current increases. The duty cycle is zero if the
I_ramp current is below about 110 μ A.
The duty cycle is limited to about 81% mainly by the reset
time and the 100 ns delay that all together represent 14% of
the period. In a 100 kHz application, the relative impact of
these times would be reduced and the maximum duty cycle
would be higher (in the range of 92%).
In fact, the high ? side on ? times are useful only during the
forward on ? times. Finally, if the duty cycle of the forward
converter is less than 80%, one can consider that the useful
post regulator duty cycle can vary between 0 and 100%.
It can also be noted that the HS MOSFET can be turned
on while the forward power switch is off, the forward
free ? wheeling MOSFET (Q2) is on and then no voltage is
applied to the post ? regulator. This is not an issue since the
MOSFETs Q2 and Q3 derive the L2 coil current so that the
I_ramp (mA)
Figure 26. HS MOSFET Duty Cycle vs. I_ramp (zoom)
RESET Block
The “reset” pin should receive the free ? wheeling drive
signal of the forward (refer to application schematic). When
this voltage exceeds the reset block threshold (2.55 V
typically), the C_ramp capacitor is grounded by an internal
switch for about 250 ns and the low ? side MOSFET is turned
on. The circuit is then initialized for a new cycle.
The voltage that is applied to the “reset” pin, may be
negative during one part of the period. The NCP4330
incorporates a negative clamp system to avoid that too
negative voltages on the pin may cause carriers injection
within the die. The negative clamp acts to force a minimum
voltage of about –0.3 V in conjunction with the external
resistor R3. It features a current capability of about 2.0 mA.
C
C_ramp
V DD
Negative
Clamp
RESET Pin
Voltage
1.55 V
Reset signal
R3
RST pin
V DD
2.55 V/
-
+
HYST COMP
250 ns
Vdelay
1
2
AND
Ctrl
3
Q?
NPN
Vdelay
Ctrl
GND
To HS and LS drivers
Figure 27. Reset Block
http://onsemi.com
10
250 ns
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