参数资料
型号: NCP4330DR2G
厂商: ON Semiconductor
文件页数: 2/17页
文件大小: 0K
描述: IC DRIVER POST REGULATION 8-SOIC
标准包装: 1
输出隔离: 非隔离
频率范围: 达 400kHz
输入电压: 5.2 V ~ 20 V
输出电压: 0.9 V ~ 23.5 V
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 剪切带 (CT)
其它名称: NCP4330DR2GOSCT
NCP4330
Converter Winding
Voltage
Synchronization
Signal
0V
2.55 V
Time
Time
Internal RESET
Signal
C_ramp Voltage
VrefH
Time
VrefL
0V
Time
High ? Side Driver
(referenced to
HS MOSFET source)
Time
Low ? Side Driver
100 ns delay
100 ns delay
Time
Figure 2. Timing Diagram(s)
DETAILED PIN DESCRIPTION(S)
Pin
Number
1
2
3
4
5
6
7
8
Name
HS_DRV
BST
RST
C_ramp
I_ramp
V DD
LS_DRV
GND
Function
“HS_DRV” is the gate driver of the high ? side MOSFET.
“BST” is the bootstrap pin. A 0.1 m F to 1.0 m F ceramic capacitor should be connected between this pin
and the node that is common to the coil and the two MOSFET. The “BST” voltage feeds the high ? side
driver (“HS_DRV”).
The “RST” pin resets the C_ramp voltage in order to synchronize the post ? regulator free ? wheeling
sequence to the forward converter demagnetization phase.
The capacitor connected to the C_ramp pin enables to adjust the delay in turning on the high ? side
MOSFET (in conjunction with “I_ramp” current).
The “I_ramp” pin receives a current supplied by a regulation means. This current adjusts the delay after
which the high ? side MOSFET is turned on. By this way, it modules the high ? side MOSFET on time in
order to regulate the output voltage.
“V DD ” is the power supply input. A 0.1 m F to 1.0 m F ceramic capacitor should be connected from this pin
to ground for decoupling.
“LS_DRV” is the driver output of the low ? side MOSFET gate.
Ground.
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