参数资料
型号: NT5DS64M8BF-6KI
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA60
封装: 1 MM PITCH, WBGA-60
文件页数: 14/79页
文件大小: 6238K
代理商: NT5DS64M8BF-6KI
NT5DS128M4BF
NT5DS128M4BT
NT5DS128M4BG
NT5DS128M4BS
NT5DS64M8BF
NT5DS64M8BT
NT5DS64M8BG
NT5DS64M8BS
NT5DS32M16BF
NT5DS32M16BT
NT5DS32M16BG
NT5DS32M16BS
512Mb DDR SDRAM
REV 1.3
11/2007
21
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operations
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened”
(activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row
in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active
command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active com-
mand to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The
minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active com-
mand to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access
overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD.
Activating a Specific Row in a Specific Bank
RA
BA
HIGH
RA = row address.
BA = bank address.
CK
CKE
CS
RAS
CAS
WE
A0-A12
BA0, BA1
Don’t Care
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