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参数资料
| 型号： | OR3L225B7PS432-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA432 |
| 封装： | EBGA-432 |
| 文件页数： | 27/77页 |
| 文件大小： | 873K |
| 代理商： | OR3L225B7PS432-DB |
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33
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
7. EXTERNAL DEVICE EXPANSION FUNCTION
The external device expansion function is for the connection of external devices to areas other than the internal
ROM, RAM and SFR. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
The following two standby functions are available for further reduction of system current consumption.
HALT mode: In this mode, the CPU operating clock is stopped.
The average current consumption can be reduced by intermittent operation by combining this mode
with the normal operation mode.
STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on the
main system clock are suspended, and only the subsystem clock is used, resulting in extremely
small power consumption.
Figure 8-1. Standby Function
Note The current consumption can be reduced by stopping the main system clock. When the CPU is operating on
the subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC) to stop the main system clock.
The STOP instruction cannot be used.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back to the
main system clock.
9. RESET FUNCTION
The following two reset methods are available.
External reset by RESET signal input
Internal reset by watchdog timer runaway time detection
Main system
clock operation
STOP mode
(Main system clock
oscillation stopped)
HALT mode
(Clock supply to CPU halted,
oscillation maintained)
Subsystem clock
operationNote
HALT modeNote
(Clock supply to CPU halted,
oscillation maintained)
Interrupt
request
Interrupt
request
Interrupt
request
HALT
instruction
HALT
instruction
STOP
instruction
CSS=1
CSS=0
相关PDF资料 |
PDF描述 |
|---|---|
| OR3L225B7PS432I-DB | FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA432 |
| OR3L225B7PS680-DB | FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA680 |
| OR3L225B7PS680I-DB | FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA680 |
| OR3L225B8PS432-DB | FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA432 |
| OR3L225B8PS680-DB | FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA680 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR3L225B8BC432-DB | 功能描述:FPGA - 现场可编程门阵列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR3L225B8BM680-DB | 功能描述:FPGA - 现场可编程门阵列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR3LP26B | 制造商:AGERE 制造商全称:AGERE 功能描述:Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| OR3LP26BBA352-DB | 功能描述:FPGA - 现场可编程门阵列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR3LP26BBM680-DB | 功能描述:FPGA - 现场可编程门阵列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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