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Lattice Semiconductor
3
Data Addendum
March 2002
ORCA OR3LxxxB Series FPGAs
Table of Contents (continued)
Figure
Page
Table
Page
Figure 1. Simplied PFU Diagram ............................... 6
Figure 3. OR3Lxxx Programmable Input/Output
Image from
ORCA Foundry.................................... 8
Table
Page
Table 1.
ORCA OR3LxxxB Series FPGAs ..................1
Table 2.
ORCA Series 3L System Performance ..........4
Table 3. Conguration Frame Size .............................. 9
Table 4. General Conguration Mode Timing
Characteristics ..................................................... 12
Table 5. Combinatorial PFU Timing Characteristics .. 13
Table 6. Sequential PFU Timing Characteristics ....... 14
Table 7. Ripple Mode PFU Timing Characteristics .... 15
Table 8. Synchronous Memory
Write Characteristics............................................ 17
Table 9. Synchronous Memory
Read Characteristics............................................ 18
Table 10. PFU Output MUX and
Direct Routing Timing Characteristics.................. 19
Table 11. Supplemental Logic and
Interconnect Cell Timing Characteristics.............. 19
Table 12. Programmable I/O
Timing Characteristics ......................................... 20
Table 13. Microprocessor Interface (MPI) Timing
Characteristics...................................................... 23
Table 14. ExpressCLK (ECLK) and Fast Clock
(FCLK) Timing Characteristics ............................ 25
Table 15. General-Purpose Clock Timing
Characteristics (Internally Generated Clock)....... 26
Table 16. OR3Lxxx ExpressCLK to
Output Delay (Pin-to-Pin) .................................... 27
Table 17. OR3Lxxx Fast Clock (FCLK) to
Output Delay (Pin-to-Pin) .................................... 28
Table 18. OR3Lxxx General System Clock
(SCLK) to Output Delay (Pin-to-Pin).................... 29
Table 19. OR3Lxxx Input to ExpressCLK (ECLK)
Fast-Capture Setup/Hold Time (Pin-to-Pin) ......... 30
Table 20. OR3Lxxx Input to Fast Clock
Setup/Hold Time (Pin-to-Pin)............................... 32
Table 21. OR3Lxxx Input to General System Clock
(SCLK) Setup/Hold Time (Pin-to-Pin) .................. 34
Table 22. Derating for Commercial/Industrial
OR3Lxxx Devices (I/O Supply VDD) .................... 36
Table 23. Derating for Commercial/Industrial
OR3Lxxx Devices (I/O Supply VDD2) .................. 36
Table 24. 208-Pin SQFP2 Pinout .............................. 38
Table 25. 240-Pin SQFP2 Pinout ............................. 41
Table 26. 352-Pin PBGA Pinout ................................ 44
Table 27. 432-Pin EBGA Pinout ............................... 49
Table 28. 680-Pin PBGAM Pinout ............................. 60
Table 29. Absolute Maximum Ratings....................... 76
Table 30. Recommended Operating Conditions ....... 76
Table 31. Electrical Characteristics ........................... 77
Table 32. Plastic Package Thermal Characteristics
for the
ORCA Series............................................ 79
Table 33. Package Coplanarity.................................. 80
Table 34. Package Parasitics .................................... 80
Table 35. Voltage Options ......................................... 87
Table 36. Temperature Options ................................. 87
Table 37. Package Options ....................................... 87
Table 38.
ORCA OR3LxxxB Series
Package Matrix .................................................... 87
ALL
DEVICES
DISCONTINUED