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参数资料
型号： ORT82G5-2F680I
厂商： Lattice Semiconductor Corporation
文件页数： 44/119页
文件大小： 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 24
系列： *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
30
Figure 16. Deskew Lanes by Aligning /A/ Columns
Mixing Half-rate, Full-rate Modes
When channel alignment is enabled, all receive channels within an alignment group should be congured at the
same rate. For example, in the ORT82G5 channels AA, AB, can be congured for twin alignment and full-rate
mode, while channels AC, AD that form an alignment group can be congured for half-rate mode. In block align-
ment mode, each receive block can be congured in either half or full-rate mode.
When channel alignment is disabled within a block, any receive channel within the block can be used in half-rate or
full-rate mode. The clocking strategy for half-rate mode in both scenarios (channel alignment enabled or disabled)
is described in the Reference Clocks and Internal Clock Distribution sections later in this data sheet.
Multi-channel Alignment Conguration
ORT42G5 Conguration
At startup, the legacy SERDES channel logic must be powered down and removed from any multi-channel align-
ment groups:
Setting bit 1 to one in registers at locations 30002, 30012, 30102, 30112, 30003, 30013, 30103 and 30113 pow-
ers down the legacy logic. (Note that the reset value for these bits is 0.)
Setting bits 4 and 5 to zero (reset condition) in the register at locations 30810 and 30910 removes the legacy
logic from any alignment group.
Register settings for multi-channel alignment are shown in Table 6.
Table 6. Multichannel Alignment Modes
To align two channels in SERDES A:
FMPU_SYNMODE_A = 00001010 (Register Location 30811)
To align two channels in SERDES B:
FMPU_SYNMODE_B = 00001010 (Register Location 30911)
To align all four channels:
FMPU_SYNMODE_A = 00001111 (Register Location 30811)
Register Bits
FMPU_SYNMODE_[A:B][0:7]
Mode
00000000
No multichannel alignment.
00001010
Twin channel alignment.
00001111
Four channel alignment.
LANE 0
K
R
RKRK
R
K
KRKR
RK
A
LANE 1
K
R
RKRK
RK
KRKR
RK
A
LANE 2
K
R
KRK
RK
KRKR
RK
A
LANE 3
K
R
RKRK
RK
KRKR
RK
A
LANE 0
K
R
RKRK
RK
KRKR
RK
A
LANE 1
K
R
RKRK
RK
KRKR
RK
A
LANE 2
K
R
RKRK
RK
KRKR
RK
A
LANE 3
K
R
RKRK
RK
KRKR
RK
A
相关PDF资料
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ORT82G5-2F680C IC FPSC TRANSCEIVER 8CH 680-BGA
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相关代理商/技术参数
参数描述
ORT82G5-2FN680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORT82G5-2FN680C1 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORT82G5-2FN680I 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORT82G5-2FN680I1 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORT82G5-3BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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